MC9S08DN60F1CLF datasheet(283/356 Pages) FREESCALE

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Chapter 15 Timer/PWM Module (S08TPMV3)

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

283

TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). If the TPM counter is

a free-running counter, then this update is made when the TPM counter changes from $FFFE

to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and

when the TPM counter changes from TPMxMODH:L to $0000.

— Center-Aligned PWM (Section 15.4.2.4, “Center-Aligned PWM Mode)

In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L

registers with the value of their write buffer after that the both bytes were written and when the

TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). If the TPM counter is

a free-running counter, then this update is made when the TPM counter changes from $FFFE

to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and

when the TPM counter changes from TPMxMODH:L to (TPMxMODH:L - 1).

5. Center-Aligned PWM (Section 15.4.2.4, “Center-Aligned PWM Mode)

— TPMxCnVH:L = TPMxMODH:L [SE110-TPM case 1]

In this case, the TPM v3 produces 100% duty cycle. Instead, the TPM v2 produces 0% duty

cycle.

— TPMxCnVH:L = (TPMxMODH:L - 1) [SE110-TPM case 2]

In this case, the TPM v3 produces almost 100% duty cycle. Instead, the TPM v2 produces 0%

duty cycle.

— TPMxCnVH:L is changed from 0x0000 to a non-zero value [SE110-TPM case 3 and 5]

In this case, the TPM v3 waits for the start of a new PWM period to begin using the new duty

cycle setting. Instead, the TPM v2 changes the channel output at the middle of the current

PWM period (when the count reaches 0x0000).

— TPMxCnVH:L is changed from a non-zero value to 0x0000 [SE110-TPM case 4]

In this case, the TPM v3 ﬁnishes the current PWM period using the old duty cycle setting.

Instead, the TPM v2 ﬁnishes the current PWM period using the new duty cycle setting.

6. Write to TPMxMODH:L registers in BDM mode (Section 15.3.3, “TPM Counter Modulo

Registers (TPMxMODH:TPMxMODL))

In the TPM v3 a write to TPMxSC register in BDM mode clears the write coherency mechanism

of TPMxMODH:L registers. Instead, in the TPM v2 this coherency mechanism is not cleared when

there is a write to TPMxSC register.

7. Update of EPWM signal when CLKSB:CLKSA = 00

In the TPM v3 if CLKSB:CLKSA = 00, then the EPWM signal in the channel output is not update

(it is frozen while CLKSB:CLKSA = 00). Instead, in the TPM v2 the EPWM signal is updated at

the next rising edge of bus clock after a write to TPMxCnSC register.

The Figure 0-1 and Figure 0-2 show when the EPWM signals generated by TPM v2 and TPM v3

after the reset (CLKSB:CLKSA = 00) and if there is a write to TPMxCnSC register.

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