MC9S08DN60F1CLF datasheet(282/356 Pages) FREESCALE

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Chapter 15 Timer/PWM Module (S08TPMV3)

MC9S08DN60 Series Data Sheet, Rev 3

282

Freescale Semiconductor

BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the

frozen TPM counter value.

— This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to

TPMxSC, TPMxCNTH or TPMxCNTL. Instead, in these conditions the TPM v2 does not clear

this read coherency mechanism.

3. Read of TPMxCnVH:L registers (Section 15.3.5, “TPM Channel Value Registers

(TPMxCnVH:TPMxCnVL))

— In TPM v3, any read of TPMxCnVH:L registers during BDM mode returns the value of the

TPMxCnVH:L register. In TPM v2, if only one byte of the TPMxCnVH:L registers was read

before the BDM mode became active, then any read of TPMxCnVH:L registers during BDM

mode returns the latched value of TPMxCNTH:L from the read buffer instead of the value in

the TPMxCnVH:L registers.

— This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to

TPMxCnSC. Instead, in this condition the TPM v2 does not clear this read coherency

mechanism.

4. Write to TPMxCnVH:L registers

— Input Capture Mode (Section 15.4.2.1, “Input Capture Mode)

In this mode the TPM v3 does not allow the writes to TPMxCnVH:L registers. Instead, the

TPM v2 allows these writes.

— Output Compare Mode (Section 15.4.2.2, “Output Compare Mode)

In this mode and if (CLKSB:CLKSA not = 0:0), the TPM v3 updates the TPMxCnVH:L

registers with the value of their write buffer at the next change of the TPM counter (end of the

prescaler counting) after the second byte is written. Instead, the TPM v2 always updates these

registers when their second byte is written.

The following procedure can be used in the TPM v3 to verify if the TPMxCnVH:L registers

were updated with the new value that was written to these registers (value in their write buffer).

...

write the new value to TPMxCnVH:L;

read TPMxCnVH and TPMxCnVL registers;

while (the read value of TPMxCnVH:L is different from the new value written to

TPMxCnVH:L)

begin

read again TPMxCnVH and TPMxCnVL;

end

...

In this point, the TPMxCnVH:L registers were updated, so the program can continue and, for

example, write to TPMxC0SC without cancelling the previous write to TPMxCnVH:L

registers.

— Edge-Aligned PWM (Section 15.4.2.3, “Edge-Aligned PWM Mode)

In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L

registers with the value of their write buffer after that the both bytes were written and when the

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