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MC9S08DN60F1CLF Datasheet(PDF) 293 Page - Freescale Semiconductor, Inc |
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MC9S08DN60F1CLF Datasheet(HTML) 293 Page - Freescale Semiconductor, Inc |
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293 / 356 page  Chapter 16 Development Support MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor 293 Figure 16-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles after starting the bit time. Figure 16-4. BDM Target-to-Host Serial Bit Timing (Logic 0) 10 CYCLES BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN TARGET MCU DRIVE AND PERCEIVED START OF BIT TIME HIGH-IMPEDANCE BKGD PIN 10 CYCLES SPEED-UP PULSE SPEEDUP PULSE EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN |
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