PCIMX536AVV8B datasheet(31/180 Pages) FREESCALE

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Electrical Characteristics

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1

Freescale Semiconductor

4.3.2.3

DDR3 Mode I/O DC Parameters

The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. The

parameters in Table 13 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

DC input Low Voltage

Vil(dc)

—

OVSS

—

Vref-0.13V

Differential Input Logic High

Vih(diff)

0.26

See Note2

Differential Input Logic Low

Vil(diff)

See Note2

-0.26

Input current (no pull-up/down)

Iin

VI = 0 V

VI=OVDD

—

0.02

1.5

12.8

290

Pull-up/Pull-down impedance Mismatch

-15

+15

240 Ohm unit calibration resolution

Ohm

Keeper Circuit Resistance

—

1253

—k

1 Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.

2 The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as

the limitations for overshoot and undershoot.

3 Use an off-chip pull resistor of less than 60k

Ω to override this keeper.

Table 13. DDR3 I/O DC Electrical Parameters

Parameters

Symbol

Test Conditions

Min

Typ

Max

Unit

High-level output voltage

Voh

—

0.8*OVDD1

1 OVDD – I/O power supply (1.425 V–1.575 V for DDR3)

——

Low-level output voltage

Vol

—

0.2*OVDD

DC input Logic High

VIH(dc)

—

Vref2+0.1

2 Vref – DDR3 external reference voltage

—OVDD

DC input Logic Low

VIL(dc)

—

OVSS

—

Vref-0.1

Differential input Logic High

VIH(diff)

—

0.2

—

See Note3

Differential input Logic Low

VIL(diff)

—

See Note3

—-0.2

Over/undershoot peak

Vpeak

—

0.4

Over/undershoot area

(above OVDD or below OVSS)

Varea

—

0.67

V x

Termination Voltage

Vtt

Vtt tracking OVDD/2

0.49*OVDD

Vref

0.51*OVDD

Input current (no pull-up/down)

Iin

VI = 0 V

VI=OVDD

—

0.09

1.75

320

Pull-up/Pull-down impedance mismatch

—

Minimum impedance

configuration

——

240

Ω unit calibration resolution

—

Keeper Circuit Resistance

—

1254

—k

Table 12. LPDDR2 I/O DC Electrical Parameters1 (continued)

PCIMX536AVV8B Datasheet(PDF) 31 Page - Freescale Semiconductor, Inc

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