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PCIMX536AVV8B Datasheet(PDF) 88 Page - Freescale Semiconductor, Inc |
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PCIMX536AVV8B Datasheet(HTML) 88 Page - Freescale Semiconductor, Inc |
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88 / 180 page ![]() i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 88 Freescale Semiconductor Electrical Characteristics 4.7.8.6.3 TFT Panel Sync Pulse Timing Diagrams Figure 46 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and the data. All the parameters shown in the figure are programmable. All controls are started by corresponding internal events—local start points. The timing diagrams correspond to inverse polarity of the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC, and DRDY signals. Figure 46. TFT Panels Timing Diagram—Horizontal Sync Pulse Figure 47 depicts the vertical timing (timing of one frame). All parameters shown in the figure are programmable. Figure 47. TFT Panels Timing Diagram—Vertical Sync Pulse DI clock VSYNC HSYNC DRDY D0 D1 IP5o IP13o IP9o IP8o IP8 IP9 Dn IP10 IP7 IP5 IP6 IPP_DISP_CLK IPP_DATA IP14 VSYNC HSYNC DRDY Start of frame End of frame IP12 IP15 IP13 IP11 |
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