PCIMX536AVV8B datasheet(64/180 Pages) FREESCALE

64 / 180 page

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1

Freescale Semiconductor

Electrical Characteristics

NOTE

To receive the reported setup/hold values, write calibration should be

perform to locate the DQS in the middle of DQ window.

Figure 29 shows the read timing parameters.

Figure 29. DDR SDRAM DQ vs. DQS and SDCLK Read Cycle

4.7

External Peripheral Interfaces Parameters

The following subsections provide information on external peripheral interfaces.

4.7.1

AUDMUX Timing Parameters

The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between

internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of

AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI

electrical specifications found within this document.

4.7.2

CSPI and ECSPI Timing Parameters

This section describes the timing parameters of the CSPI and ECSPI blocks. The CSPI and ECSPI have

separate timing parameters for master and slave modes. The nomenclature used with the CSPI / ECSPI

modules and the respective routing of these signals is shown in Table 40.

Table 40. CSPI Nomenclature and Routing

Block Instance

I/O Access

ECSPI-1

GPIO, KPP, DISP0_DAT, CSI0_DAT and EIM_D through IOMUXC

ECSPI-2

DISP0_DAT, CSI0_DAT and EIM through IOMUXC

CSPI

DISP0_DAT, EIM_A/D, SD1 and SD2 through IOMUXC

SDCLK

SDCLK_B

DQS (input)

DQ (input)

DATA

DDR26

DDR27

PCIMX536AVV8B Datasheet(PDF) 64 Page - Freescale Semiconductor, Inc