PCIMX536AVV8B datasheet(90/180 Pages) FREESCALE

90 / 180 page

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1

Freescale Semiconductor

Electrical Characteristics

The maximal accuracy of UP/DOWN edge of controls is:

IP5o

Offset of IPP_DISP_CLK

Todicp

DISP_CLK_OFFSET

× Tdiclk

DISP_CLK_OFFSET—offset of

IPP_DISP_CLK edges from local start

point, in DI_CLK

×2

(0.5 DI_CLK Resolution)

Defined by DISP_CLK counter

IP13o Offset of VSYNC

Tovs

VSYNC_OFFSET

× Tdiclk

VSYNC_OFFSET—offset of Vsync edges

from a local start point, when a Vsync

should be active, in DI_CLK

×2

(0.5 DI_CLK Resolution).The

VSYNC_OFFSET should be built by

suitable DI’s counter.

IP8o

Offset of HSYNC

Tohs

HSYNC_OFFSET

× Tdiclk

HSYNC_OFFSET—offset of Hsync edges

from a local start point, when a Hsync

should be active, in DI_CLK

×2

(0.5 DI_CLK Resolution).The

HSYNC_OFFSET should be built by

suitable DI’s counter.

IP9o

Offset of DRDY

Todrdy

DRDY_OFFSET

× Tdiclk

DRDY_OFFSET—offset of DRDY edges

from a suitable local start point, when a

corresponding data has been set on the

bus, in DI_CLK

×2

(0.5 DI_CLK Resolution)

The DRDY_OFFSET should be built by

suitable DI’s counter.

1 Display interface clock period immediate value.

DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK.

DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency

Display interface clock period average value.

2 DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the

counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by

corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance

between HSYNCs is a SCREEN_WIDTH.

Table 57. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)

Parameter

Symbol

Value

Description

Unit

Tdicp

diclk

DISP_CLK_PERIOD

DI_CLK_PERIOD

----------------------------------------------------

for integer

DISP_CLK_PERIOD

DI_CLK_PERIOD

----------------------------------------------------

diclk

floor

DISP_CLK_PERIOD

DI_CLK_PERIOD

----------------------------------------------------

0.5

⎝⎠

⎛⎞

for fractional

DISP_CLK_PERIOD

DI_CLK_PERIOD

----------------------------------------------------

⎩

⎪

⎨

⎪

⎧

Tdicp

diclk

DISP_CLK_PERIOD

DI_CLK_PERIOD

----------------------------------------------------

Accuracy

0.5

diclk

() 0.62ns

PCIMX536AVV8B Datasheet(PDF) 90 Page - Freescale Semiconductor, Inc

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