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PIC16F1526 Datasheet(PDF) 211 Page - Microchip Technology |
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PIC16F1526 Datasheet(HTML) 211 Page - Microchip Technology |
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211 / 354 page  2011 Microchip Technology Inc. Preliminary DS41458A-page 211 PIC16(L)F1526/27 21.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSPx clock is much faster than the system clock. In Slave mode, when MSSPx interrupts are enabled, after the master completes sending data, an MSSPx interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSPx inter- rupts should be disabled. In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmis- sion/reception will remain in that state until the device wakes. After the device returns to Run mode, the mod- ule will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSPx interrupt flag bit will be set and if enabled, will wake the device. TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELF ANSF7 ANSF6 ANSF5 ANSF4 ANSF3 ANSF2 ANSF1 ANSF0 136 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 80 PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 81 PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 84 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 85 PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 88 SSP1BUF MSSPx Receive Buffer/Transmit Register 205* SSP2BUF MSSPx Receive Buffer/Transmit Register 205* SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 251 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 251 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 253 SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 253 SSP1STAT SMP CKE D/A PS R/W UA BF 249 SSP2STAT SMP CKE D/A PS R/W UA BF 249 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 126 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 129 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 135 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx in SPI mode. * Page provides register information. |
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