PIC16F1526 datasheet(82/354 Pages) MICROCHIP

82 / 354 page

PIC16(L)F1526/27

DS41458A-page 82

Preliminary

 2011 Microchip Technology Inc.

7.6.3

PIE2 REGISTER

The PIE2 register contains the interrupt enable bits, as

shown in Register 7-3.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0

U-0

R/W-0/0

OSFIE

TMR5GIE

TMR3GIE

—

BCL1IE

TMR10IE

TMR8IE

CCP2IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

OSFIE:

Oscillator Fail Interrupt Enable bit

= Enables the Oscillator Fail interrupt

= Disables the Oscillator Fail interrupt

bit 6

TMR5GIE:

Timer5 Gate Interrupt Enable bit

= Enables the Timer5 Gate Acquisition interrupt

= Disables the Timer5 Gate Acquisition interrupt

bit 5

TMR3GIE:

Timer3 Gate Interrupt Enable bit

= Enables the Timer3 Gate Acquisition interrupt

= Disables the Timer3 Gate Acquisition interrupt

bit 4

Unimplemented:

Read as ‘0’

bit 3

BCL1IE:

MSSP1 Bus Collision Interrupt Enable bit

= Enables the MSSP1 Bus Collision Interrupt

= Disables the MSSP1 Bus Collision Interrupt

bit 2

TMR10IE:

TMR10 to PR10 Match Interrupt Enable bit

= Enables the Timer10 to PR10 match interrupt

= Disables the Timer10 to PR10 match interrupt

bit 1

TMR8IE:

TMR8 to PR8 Match Interrupt Enable bit

= Enables the Timer8 to PR8 match interrupt

= Disables the Timer8 to PR8 match interrupt

bit 0

CCP2IE:

CCP2 Interrupt Enable bit

= Enables the CCP2 interrupt

= Disables the CCP2 interrupt

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