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PIC16F1526 Datasheet(PDF) 84 Page - Microchip Technology |
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PIC16F1526 Datasheet(HTML) 84 Page - Microchip Technology |
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84 / 354 page ![]() PIC16(L)F1526/27 DS41458A-page 84 Preliminary 2011 Microchip Technology Inc. 7.6.5 PIE4 REGISTER The PIE4 register contains the interrupt enable bits, as shown in Register 7-5. Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. REGISTER 7-5: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCP10IE: CCP10 Interrupt Enable bit 1 = Enables the CCP10 interrupt 0 = Disables the CCP10 interrupt bit 6 CCP9IE: CCP9 Interrupt Enable bit 1 = Enables the CCP9 interrupt 0 = Disables the CCP9 interrupt bit 5 RC2IE: USART2 Receive Interrupt Enable bit 1 = Enables the USART2 receive interrupt 0 = Disables the USART2 receive interrupt bit 4 TX2IE: USART2 Transmit Interrupt Enable bit 1 = Enables the USART2 transmit interrupt 0 = Disables the USART2 transmit interrupt bit 3 CCP8IE: CCP8 Interrupt Enable bit 1 = Enables the CCP8 interrupt 0 = Disables the CCP8 interrupt bit 2 CCP7IE: CCP7 Interrupt Enable bit 1 = Enables the CCP7 interrupt 0 = Disables the CCP7 interrupt bit 1 BCL2IE: MSSP2 Bus Collision Interrupt Enable bit 1 = Enables the MSSP2 Bus Collision Interrupt 0 = Disables the MSSP2 Bus Collision Interrupt bit 0 SSP2IE: Synchronous Serial Port (MSSP2) Interrupt Enable bit 1 = Enables the MSSP2 interrupt 0 = Disables the MSSP2 interrupt |
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