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PIC16F1526 Datasheet(PDF) 57 Page - Microchip Technology |
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PIC16F1526 Datasheet(HTML) 57 Page - Microchip Technology |
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57 / 354 page ![]() 2011 Microchip Technology Inc. Preliminary DS41458A-page 57 PIC16(L)F1526/27 5.2.2.3 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The output of the 16 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software: •16 MHz •8 MHz •4 MHz •2 MHz •1 MHz • 500 kHz (Default after Reset) • 250 kHz • 125 kHz • 62.5 kHz • 31.25 kHz • 31 kHz (LFINTOSC) The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These dupli- cate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transi- tion times can be obtained between frequency changes that use the same oscillator source. 5.2.2.4 Internal Oscillator Clock Switch Timing When switching between the HFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 5-7). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. IRCF<3:0> bits of the OSCCON register are modified. 2. If the new clock is shut down, a clock start-up delay is started. 3. Clock switch circuitry waits for a falling edge of the current clock. 4. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. 5. The new clock is now active. 6. The OSCSTAT register is updated as required. 7. Clock switch is complete. See Figure 5-7 for more details. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 5-1. Start-up delay specifications are located in the oscillator tables of Section 25.0 “Electrical Specifications” Note: Following any Reset, the IRCF<3:0> bits of the OSCCON register are set to ‘0111’ and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency. |
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