PIC16F1526 datasheet(70/354 Pages) MICROCHIP

70 / 354 page

PIC16(L)F1526/27

DS41458A-page 70

Preliminary

 2011 Microchip Technology Inc.

6.3

Low-Power Brown-out Reset

(LPBOR)

The Low-Power Brown-Out Reset (LPBOR) is an

essential part of the Reset subsystem. Refer to

Figure 6-1 to see how the BOR interacts with other

modules.

The LPBOR is used to monitor the external VDD pin.

When too low of a voltage is detected, the device is

held in Reset. When this occurs, a register bit (BOR) is

changed to indicate that a BOR Reset has occurred.

The same bit is set for both the BOR and the LPBOR.

Refer to Register 6-2.

6.3.1

ENABLING LPBOR

The LPBOR is controlled by the LPBOR bit of

Configuration Word 2. When the device is erased, the

LPBOR module defaults to disabled.

6.3.1.1

LPBOR Module Output

The output of the LPBOR module is a signal indicating

whether or not a Reset is to be asserted. This signal is

to be OR’d together with the Reset signal of the BOR

module to provide the generic BOR signal which goes

to the PCON register and to the power control block.

6.4

MCLR

The MCLR is an optional external input that can reset

the device. The MCLR function is controlled by the

MCLRE bit of Configuration Word 1 and the LVP bit of

Configuration Word 2 (Register 4-2).

6.4.1

MCLR ENABLED

When MCLR is enabled and the pin is held low, the

device is held in Reset. The MCLR pin is connected to

VDD through an internal weak pull-up.

The device has a noise filter in the MCLR Reset path.

The filter will detect and ignore small pulses.

6.4.2

MCLR DISABLED

When MCLR is disabled, the pin functions as a general

purpose input and the internal weak pull-up is under

software control. See Section 12.6 “PORTE Registers”

for more information.

6.5

Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware

does not issue a CLRWDT instruction within the time-out

period. The TO and PD bits in the STATUS register are

changed to indicate the WDT Reset. See Section 10.0

“Watchdog Timer”

for more information.

6.6

RESET

Instruction

A RESET instruction will cause a device Reset. The RI

bit in the PCON register will be set to ‘0’. See Table 6-4

for default conditions after a RESET instruction has

occurred.

6.7

Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or

Underflows. The STKOVF or STKUNF bits of the PCON

enabled by setting the STVREN bit in Configuration

Word 2. See Section 3.4.2 “Overflow/Underflow

Reset”

for more information.

6.8

Programming Mode Exit

Upon exit of Programming mode, the device will

behave as if a POR had just occurred.

6.9

Power-Up Timer

The Power-up Timer optionally delays device execution

after a BOR or POR event. This timer is typically used to

allow VDD to stabilize before allowing the device to start

running.

The Power-up Timer is controlled by the PWRTE bit of

Configuration Word 1.

6.10

Start-up Sequence

Upon the release of a POR or BOR, the following must

occur before the device will begin executing:

Power-up Timer runs to completion (if enabled).

Oscillator start-up timer runs to completion (if

required for oscillator source).

MCLR must be released (if enabled).

The total time-out will vary based on oscillator configu-

ration and Power-up Timer configuration. See

Section 5.0 “Oscillator Module (With Fail-Safe

Clock Monitor)”

for more information.

The Power-up Timer and oscillator start-up timer run

independently of MCLR Reset. If MCLR is kept low long

enough, the Power-up Timer and oscillator start-up

timer will expire. Upon bringing MCLR high, the device

will begin execution immediately (see Figure 6-3). This

is useful for testing purposes or to synchronize more

than one device operating in parallel.

TABLE 6-2:

MCLR CONFIGURATION

MCLRE

LVP

MCLR

Disabled

Enabled

Note:

A Reset does not drive the MCLR pin low.

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