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PIC16F1526 Datasheet(PDF) 87 Page - Microchip Technology |
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PIC16F1526 Datasheet(HTML) 87 Page - Microchip Technology |
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87 / 354 page ![]() 2011 Microchip Technology Inc. Preliminary DS41458A-page 87 PIC16(L)F1526/27 7.6.8 PIR3 REGISTER The PIR3 register contains the interrupt flag bits, as shown in Register 7-8. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 7-8: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCP6IF CCP5IF CCP4IF CCP3IF TMR6IF TMR5IF TMR4IF TMR3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCP6IF: CCP6 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 CCP5IF: CCP5 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 CCP4IF: CCP4 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 CCP3IF: CCP3 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 TMR6IF: TMR6 to PR6 Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 TMR5IF: Timer5 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR3IF: Timer3 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending |
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