PIC16F1526 datasheet(83/354 Pages) MICROCHIP

83 / 354 page

 2011 Microchip Technology Inc.

Preliminary

DS41458A-page 83

PIC16(L)F1526/27

7.6.4

PIE3 REGISTER

The PIE3 register contains the interrupt enable bits, as

shown in Register 7-4.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

R/W-0/0

CCP6IE

CCP5IE

CCP4IE

CCP3IE

TMR6IE

TMR5IE

TMR4IE

TMR3IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

CCP6IE:

CCP6 Interrupt Enable bit

= Enables the CCP6 interrupt

= Disables the CCP6 interrupt

bit 6

CCP5IE:

CCP5 Interrupt Enable bit

= Enables the CCP5 interrupt

= Disables the CCP5 interrupt

bit 5

CCP4IE:

CCP4 Interrupt Enable bit

= Enables the CCP4 interrupt

= Disables the CCP4 interrupt

bit 4

CCP3IE:

CCP3 Interrupt Enable bit

= Enables the CCP3 interrupt

= Disables the CCP3 interrupt

bit 3

TMR6IE:

TMR6 to PR6 Match Interrupt Enable bit

= Enables the TMR6 to PR6 Match interrupt

= Disables the TMR6 to PR6 Match interrupt

bit 2

TMR5IE:

Timer5 Overflow Interrupt Enable bit

= Enables the Timer5 overflow interrupt

= Disables the Timer5 overflow interrupt

bit 1

TMR4IE:

TMR4 to PR4 Match Interrupt Enable bit

= Enables the TMR4 to PR4 Match interrupt

= Disables the TMR4 to PR4 Match interrupt

bit 0

TMR3IE:

Timer3 Overflow Interrupt Enable bit

= Enables the Timer3 overflow interrupt

= Disables the Timer3 overflow interrupt

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