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PIC16F1526 Datasheet(PDF) 263 Page - Microchip Technology |
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PIC16F1526 Datasheet(HTML) 263 Page - Microchip Technology |
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263 / 354 page  2011 Microchip Technology Inc. Preliminary DS41458A-page 263 PIC16(L)F1526/27 FIGURE 22-5: ASYNCHRONOUS RECEPTION Start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 Stop bit Start bit Start bit bit 7/8 Stop bit RXx/DTx pin Reg Rcv Buffer Reg Rcv Shift Read Rcv Buffer Reg RCxREG RCxIF (Interrupt Flag) OERR bit CREN Word 1 RCxREG Word 2 RCxREG Stop bit Note: This timing diagram shows three words appearing on the RXx/DTx input. The RCxREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. RCIDL TABLE 22-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 266 BAUD2CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 266 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93 PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 94 PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 97 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 98 PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 97 RC1REG EUSART1 Receive Register 260* RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 265 RC2REG EUSART2 Receive Register 260* RC2STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 265 SP1BRGL EUSART1 Baud Rate Generator, Low Byte 267* SP1BRGH EUSART1 Baud Rate Generator, High Byte 267* SP2BRGL EUSART2 Baud Rate Generator, Low Byte 267* SP2BRGH EUSART2 Baud Rate Generator, High Byte 267* TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 134 TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 264 TX2STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 264 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception. * Page provides register information. |
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