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PIC16F1526 Datasheet(PDF) 350 Page - Microchip Technology |
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PIC16F1526 Datasheet(HTML) 350 Page - Microchip Technology |
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350 / 354 page  PIC16(L)F1526/27 DS41458A-page 350 Preliminary 2011 Microchip Technology Inc. Bus Collision for Transmit and Acknowledge............ 242 Capture/Compare/PWM (CCP)................................. 321 CLKOUT and I/O....................................................... 317 Clock Synchronization .............................................. 230 Clock Timing ............................................................. 316 Fail-Safe Clock Monitor (FSCM) ................................. 63 First Start Bit Timing ................................................. 234 I2C Bus Data ............................................................. 329 I2C Bus Start/Stop Bits.............................................. 328 I2C Master Mode (7 or 10-Bit Transmission) ............ 237 I2C Master Mode (7-Bit Reception)........................... 239 I2C Stop Condition Receive or Transmit Mode ......... 241 INT Pin Interrupt.......................................................... 78 Internal Oscillator Switch Timing................................. 58 Repeat Start Condition.............................................. 235 Reset Start-up Sequence............................................ 71 Reset, WDT, OST and Power-up Timer ................... 318 Send Break Character Sequence ............................. 275 SPI Master Mode (CKE = 1, SMP = 1) ..................... 326 SPI Mode (Master Mode).......................................... 207 SPI Slave Mode (CKE = 0) ....................................... 327 SPI Slave Mode (CKE = 1) ....................................... 327 Synchronous Reception (Master Mode, SREN) ....... 280 Synchronous Transmission....................................... 277 Synchronous Transmission (Through TXEN) ........... 277 Timer0 and Timer1 External Clock ........................... 320 Timer1/3/5 Incrementing Edge.................................. 173 Two Speed Start-up .................................................... 61 USART Synchronous Receive (Master/Slave) ......... 324 USART Synchronous Transmission (Master/Slave) . 324 Wake-up from Interrupt ............................................... 92 Timing Parameter Symbology........................................... 315 Timing Requirements I2C Bus Data ............................................................. 330 SPI Mode .................................................................. 328 TMR0 Register .................................................................... 30 TMR1H Register ................................................................. 30 TMR1L Register .................................................................. 30 TMR2 Register .............................................................. 30, 35 TRIS .................................................................................. 302 TRISA................................................................................ 119 TRISA Register ........................................................... 30, 120 TRISB................................................................................ 122 TRISB Register ........................................................... 30, 123 TRISC ............................................................................... 125 TRISC Register ........................................................... 30, 126 TRISD ............................................................................... 128 TRISD Register ........................................................... 30, 129 TRISE................................................................................ 131 TRISE Register ........................................................... 30, 132 TRISF................................................................................ 134 TRISF Register ................................................................. 135 TRISG ............................................................................... 137 TRISG Register................................................................. 138 Two-Speed Clock Start-up Mode ........................................ 60 TXCON (Timer2/4/6/8/10) Register................................... 181 TxCON Register................................................................ 176 TxGCON Register ............................................................. 177 TXREG.............................................................................. 257 TXREG Register ................................................................. 31 TXSTA Register .......................................................... 31, 264 BRGH Bit .................................................................. 267 U USART Synchronous Master Mode Requirements, Synchronous Receive .............. 324 Requirements, Synchronous Transmission...... 324 Timing Diagram, Synchronous Receive ........... 324 Timing Diagram, Synchronous Transmission... 324 V VREF. SEE ADC Reference Voltage VREGCON Register ........................................................... 94 W Wake-up on Break ............................................................ 273 Wake-up Using Interrupts ................................................... 92 Watchdog Timer (WDT)...................................................... 70 Associated Registers ................................................ 100 Configuration Word w/ Watchdog Timer................... 100 Modes......................................................................... 98 Specifications ........................................................... 320 WCOL ....................................................... 233, 236, 238, 240 WCOL Status Flag.................................... 233, 236, 238, 240 WDTCON Register ............................................................. 99 WPUB Register................................................................. 124 WPUD Register ................................................................ 130 WPUE Register................................................................. 133 Write Protection .................................................................. 49 WWW Address ................................................................. 351 WWW, On-Line Support ....................................................... 9 |
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