WM8758CBGEFLSLASHV datasheet(61/90 Pages) WOLFSON

61 / 90 page

Production Data

WM8758B

PD, Rev 4.4, January 2012

DIGITAL AUDIO INTERFACES

The audio interface has four pins:



ADCDAT: ADC data output



DACDAT: DAC data input



LRC: Data Left/Right alignment clock



BCLK: Bit clock, for synchronisation

The clock signals BCLK, and LRC can be outputs when the WM8758B operates as a master, or

inputs when it is a slave (see Master and Slave Mode Operation, below).

Five different audio data formats are supported:



Left justified



Right justified



DSP mode A



DSP mode B

All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the

Electrical Characteristic section for timing information.

MASTER AND SLAVE MODE OPERATION

The WM8758B audio interface may be configured as either master or slave. As a master interface

device the WM8758B generates BCLK and LRC and thus controls sequencing of the data transfer on

ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In

slave mode (MS=0), the WM8758B responds with data to clocks it receives over the digital audio

interfaces.

In master mode, the BCLK and LRC clocks are not stopped when the ADC’s are disabled using

outputs the last word of data which was transmitted when the ADC was disabled. To prevent this in

master mode, it is necessary to disable the ADC’s R2[1:0] and DAC’s R3{[:0] and remove the MCLK

input clock OR by switching the digital audio interface to slave mode.

AUDIO DATA FORMATS

In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRC

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRC transition.

Figure 31 Left Justified Audio Interface (assuming n-bit word length)

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition.

All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and

sample rate, there may be unused BCLK cycles after each LRC transition.

WM8758CBGEFL/V Datasheet(PDF) 61 Page - Wolfson Microelectronics plc

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