WM8758CBGEFLSLASHV datasheet(26/90 Pages) WOLFSON

26 / 90 page

WM8758B

Production Data

PD, Rev 4.4, January 2012

CLOCKING SCHEMES

WM8758B offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided to

the DAC and ADC. A PLL is included which may be used to generate these clocks in the event that

they are not available from the system controller. This PLL can accept a range of common input clock

frequencies between 8MHz and 50MHz to generate high quality audio clocks. If this PLL is not

required for generation of these clocks, it can be reconfigured to generate alternative clocks which

may then be output on the GPIO pins and used elsewhere in the system.

POWER CONTROL

The design of the WM8758B has given much attention to power consumption without compromising

performance. It operates at very low voltages, includes the ability to power off any unused parts of the

circuitry under software control, and includes standby and power off modes.

INPUT SIGNAL PATH

The WM8758B has a number of flexible analogue inputs. There are two input channels, Left and

Right, each of which consists of an input PGA stage followed by a boost/mix stage which drives into

the hi-fi ADC. Each input path has three input pins which can be configured in a variety of ways to

accommodate single-ended, differential or dual differential microphones. A bypass path exists from

the output of the boost/mix stage into the output left/right mixers.

MICROPHONE INPUTS

The WM8758B can accommodate a variety of microphone configurations including single ended and

differential inputs. The inputs to the left differential input PGA are LIN, LIP and L2. The inputs to the

right differential input PGA are RIN, RIP and R2.

In single-ended microphone input configuration the microphone signal should be input to LIN or RIN

and the internal NOR gate configured to clamp the non-inverting input of the input PGA to VMID.

In differential mode the larger signal should be input to LIP or RIP and the smaller (e.g. noisy ground

connection) should be input to LIN or RIN.

Figure 12 Microphone Input PGA Circuit

The input PGAs are enabled by the IPPGAENL/R register bits.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power

Management

INPPGAENL

Left channel input PGA enable

0 = disabled

1 = enabled

INPPGAENR

Right channel input PGA enable

0 = disabled

1 = enabled

Table 4 Input PGA Enable Register Settings

WM8758CBGEFL/V Datasheet(PDF) 26 Page - Wolfson Microelectronics plc

WM8758CBGEFL/V Datasheet(HTML) 26 Page - Wolfson Microelectronics plc

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