| Electronic Components Datasheet Search |
|
WM8758CBGEFL/V Datasheet(PDF) 75 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8758CBGEFL/V Datasheet(HTML) 75 Page - Wolfson Microelectronics plc |
|
75 / 90 page ![]() Production Data WM8758B w PD, Rev 4.4, January 2012 75 POWER SUPPLIES The WM8758B requires four separate power supplies: AVDD1 and AGND1: Analogue supply, powers all internal analogue functions and output drivers LOUT1, ROUT1, OUT3 and OUT4. AVDD1 must be between 2.5V and 3.6V and has the most significant impact on overall power consumption (except for power consumed in the headphones). Higher AVDD will improve audio quality. AVDD2 and AGND2: Output driver supplies, power LOUT2 and ROUT2. AVDD2 must be between 2.5V and 3.6V. AVDD2 can be tied to AVDD1, but it requires separate layout and decoupling capacitors to curb harmonic distortion. DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces. DCVDD must be between 1.71V and 3.6V, and has no effect on audio quality. The return path for DCVDD is DGND, which is shared with DBVDD. DBVDD must be between 1.71V and 3.6V. DBVDD return path is through DGND. It is possible to use the same supply voltage for all four supplies. However, digital and analogue supplies should be routed and decoupled separately on the PCB to keep digital switching noise out of the analogue signal paths. POWER MANAGEMENT SAVING POWER BY REDUCING OVERSAMPLING RATE The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR128 the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R14 ADC control 3 ADCOSR128 0 ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) Table 53 ADC Oversampling Rate Selection LOW POWER MODE If only DAC or ADC functionality is required, the WM8758B can be put into a low power mode. In this mode, the DSP core runs at half of the normal rate, reducing digital power consumption of the core by half. For DAC low power only, 3D enhancement with 2-Band equalizer functionality is permitted, where only Band 1 (low shelf) and Band 5 (high shelf) can be used. For ADC low power, the equalizer and 3D cannot be used. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R7 Additional Ctrl 8 M128ENB 0 0 = low power mode enabled 1 = low power mode disabled Table 54 DSP Core Low Power Mode Control |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |