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WM8758CBGEFL/V Datasheet(PDF) 76 Page - Wolfson Microelectronics plc |
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WM8758CBGEFL/V Datasheet(HTML) 76 Page - Wolfson Microelectronics plc |
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76 / 90 page ![]() WM8758B Production Data w PD, Rev 4.4, January 2012 76 There are 3 modes of low power operation, as detailed below. The device will not enter low power unless in one of these register configurations, regardless of M128ENB. FUNCTION REGISTER BITS SETTING DESCRIPTION ADC low power M128ENB ADCENL ADCENR DACENL DACENR EQ3DMODE 0 1 1 0 0 1 (DAC path) Either or both of ADCENL and ADCENR must be set (mono or stereo mode) DAC low power M128ENB ADCENL ADCENR DACENL DACENR 0 0 0 1 1 Either or both of DACENL and DACENR must be set (mono or stereo mode) EQ3DMODE = 0: EQ in ADC path EQ3DMODE = 1: EQ in DAC path Table 55 DSP Core Low Power Modes for ADC Only and DAC Only Modes VMID The analogue equalizer will not operate unless VMID is enabled. The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the startup time of the VMID circuit. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1 Power management 1 1:0 VMIDSEL 00 Reference string impedance to VMID pin (Determines startup time): 00 = off (250kΩ VMID to AGND1) 01 = 100kΩ 10 = 500kΩ 11 = 10kΩ (for fast startup) Table 56 VMID Impedance Control BIASEN The analogue amplifiers will not operate unless BIASEN is enabled. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1 Power management 1 3 BIASEN 0 Analogue amplifier bias control 0 = disabled 1 = enabled Table 57 Analogue Bias Control HALFOPBIAS HALFOPBIAS halves the bias current to the output drivers (OUT1, OUT2, OUT3). Setting HALFOPBIAS will reduce the quiescent current from AVDD by 0.5mA but will degrade the THD+N significantly. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R61 Bias Control 0 HALFO PBIAS 0 HALFOPBIAS (Do not use) 0 = disabled 1 = enabled (Reduces AVDD current by 0.5mA) Table 58 HALFOPBIAS Control Wolfson’s recommendation is: Do not use HALFOPBIAS |
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