WM8758CBGEFLSLASHV datasheet(64/90 Pages) WOLFSON

64 / 90 page

WM8758B

Production Data

PD, Rev 4.4, January 2012

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Audio

Interface

Control

MONO

Selects between stereo and mono

device operation:

0 = Stereo device operation

1 = Mono device operation. Data

appears in ‘left’ phase of LRC.

ADCLRSWAP

Controls whether ADC data appears in

‘right’ or ‘left’ phases of LRC clock:

0 = ADC left data appear in ‘left’ phase

of LRC and right data in ‘right’ phase

1 = ADC left data appear in ‘right’ phase

of LRC and right data in ‘left’ phase

DACLRSWAP

Controls whether DAC data appears in

‘right’ or ‘left’ phases of LRC clock:

0 = DAC left data appear in ‘left’ phase

of LRC and right data in ‘right’ phase

1 = DAC left data appear in ‘right’ phase

of LRC and right data in ‘left’ phase

4:3

FMT

Audio interface Data Format Select:

00 = Right Justified

01 = Left Justified

10 = I

2S format

11 = DSP/PCM mode

6:5

Word length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits (see note)

LRP

RJ, LJ & I

2S modes – LRC polarity

0 = normal LRC polarity

1 = invert LRC polarity

DSP Mode – mode A/B select

0 = MSB is available on 2

nd BCLK rising

edge after LRC rising edge (mode A)

1 = MSB is available on 1

st BCLK rising

edge after LRC rising edge (mode B)

BCP

BCLK polarity

0 = normal

1 = inverted

LOOPBACK

Digital loopback function

0 = No loopback

1 = Loopback enabled, ADC data output

is fed directly into DAC data input.

Table 42 Audio Interface Control

Note:

Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the

device will operate in 24-bit mode.

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised

below.

LRC are outputs. The frequency of BCLK and LRC in master mode is controlled with BCLKDIV.

These are divided down versions of master clock. This may result in short BCLK pulses at the end of

a LRC if there is a non-integer ratio of BCLKs to LRC clocks.

WM8758CBGEFL/V Datasheet(PDF) 64 Page - Wolfson Microelectronics plc

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