LM98714CCMTSLASHNOPB datasheet(30/114 Pages) TI1

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INCLK = ADCCLK

PIXPHASE0 (default)

Main Configutation Reg 1

Bit[1:0] = 2'b00

ADCCLK

PIXPHASE0 = TSYSCLK * 0

PIXPHASE1

Main Configutation Reg 1

Bit[1:0] = 2'b01

PIXPHASE2

Main Configutation Reg 1

Bit[1:0] = 2'b10

PIXPHASE3

Main Configutation Reg 1

Bit[1:0] = 2'b11

SYSCLK = 7 * fADCCLK = 21 * fPIXCLK

(In Mode 3)

INCLK = PIXCLK

SYSCLK

(Internal system clock)

PIXPHASE1 = TSYSCLK * 3

PIXPHASE2 = TSYSCLK * 7

PIXPHASE3 = TSYSCLK * 10

PIXCLK

CCD Output = ?

CCD Output

(Input to AFE)

The CCD output will usually have a measurable delay with respect to the input clock to the AFE. The AFE’s internal sampling cl

ocks are based on one of four PIXPHASE clocks. These

PIXPHASE settings provide coarse adjustment of the internal AFE clock domain to best match the phase of the incoming CCD signal

. Fine adjustment of the sampling clocks is discussed

in another section. In this example above, PIXPHASE2 appears to provide the closest match for the incoming CCD signal.

(Output from CCD

Timing Generator)

SHFP

LM98714

SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014

www.ti.com

The four available Coarse Pixel Phases (PIXPHASE0 - PIXPHASE3) are depicted in Figure 19 (Mode 3),

Figure 20 (Mode 2) and Figure 21 (Mode 1). Also shown in the diagrams are the external input clock (INCLK)

and a typical CCD output delayed from the input clock.

Figure 19. Mode 3 Coarse Pixel Adjustment

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