LM98714CCMTSLASHNOPB datasheet(33/114 Pages) TI1

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LM98714

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SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014

Internal Sample Timing

A typical CCD input signal is depicted in Figure 22 and Figure 23. Also shown are the internally generated

SAMPLE and CLAMP pulses. These signals provide the sampling points of the input signal (OSX). The timing of

SAMPLE and CLAMP is derived from an internal system clock (SYSCLK).

The pixel’s reference level input (depicted as VREF) is captured by the falling edge of the CLAMP pulse. In

Sample/Hold Mode the VREF input is a sample of the VCLP DC voltage. In CDS Mode the CLAMP pulse samples

the pedestal Level of the CCD output waveform.

The pixel’s signal level input (depicted as VSIG) is captured by the SAMPLE pulse. In either Sample/Hold or CDS

Mode, the VSIG input is the signal level of the CCD output waveform.

The LM98714 provides fine adjustment of the CLAMP and SAMPLE pulse placement within the pixel period. This

allows the user to program the optimum location of the CLAMP and SAMPLE falling edges. In CDS mode, both

CLAMP and SAMPLE are independently adjustable for each channel in use. In Sample/Hold mode, CLAMP is

coincident with SAMPLE by default, but is also independently adjustable. The available fine tuning locations for

CLAMP and SAMPLE are shown in Figure 24 through Figure 29 for each sampling mode (CDS or S/H) and

channel mode (3, 2, or 1 Channel).

Figure 22. Pixel Sampling in CDS Mode

Figure 23. Pixel Sampling in S/H Mode

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LM98714CCMT/NOPB Datasheet(PDF) 33 Page - Texas Instruments