WM1811A datasheet(40/328 Pages) WOLFSON

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WM1811A

Production Data

PD, November 2013, Rev 4.1

MICROPHONE INPUTS

Up to four analogue microphones can be connected to the WM1811A, either in single-ended or

differential mode. A dedicated PGA is provided for each microphone input. Two low noise microphone

bias circuits are provided, reducing the need for external components.

For single-ended microphone inputs, the microphone signal is connected to the inverting input of the

PGAs (IN1LN, IN2LN, IN1RN or IN2RN). The non-inverting inputs of the PGAs are internally

connected to VMID in this configuration. The non-inverting input pins IN1LP, IN2LP, IN1RP and

IN2RP are free to be used as line connections to the input or output mixers in this configuration.

For differential microphone inputs, the non-inverted microphone signal is connected to the non-

inverting input of the PGAs (IN1LP, IN2LP, IN1RP or IN2RP), whilst the inverted (or ‘noisy ground’)

signal is connected to the inverting input pins (IN1LN, IN2LN, IN1RN and IN2RN).

The gain of the input PGAs is controlled via register settings, as defined in Table 4. Note that the input

impedance of both inverting and non-inverting inputs changes with the input PGA gain setting, as

described under “Electrical Characteristics”.See also the “Applications Information” for details of input

resistance at all PGA Gain settings.

The microphone input configurations are illustrated in Figure 8 and Figure 9. Note that any PGA input

pin that is used in either microphone configuration is not available for use as a line input path at the

same time.

MIC

GND

input

mixers

PGA

VMID

MICBIAS

IN1LN,

IN2LN,

IN1RN,

IN2RN

IN1LP,

IN2LP,

IN1RP,

IN2RP

Figure 8 Single-Ended Microphone Input

Figure 9 Differential Microphone Input

MICROPHONE BIAS CONTROL

There are two MICBIAS generators which provide low noise reference voltages suitable for powering

silicon (MEMS) microphones or biasing electret condenser (ECM) type microphones via an external

resistor. Refer to the “Applications Information” section for recommended external components.

The MICBIAS outputs can be independently enabled using the MICB1_ENA and MICB2_ENA register

bits. Under default conditions, a smooth pop-free profile of the MICBIAS outputs is implemented when

MICB1_ENA or MICB2_ENA is enabled or disabled; a faster transition can be selected by setting the

MICB1_RATE and MICB2_RATE registers as described in Table 1.

When a MICBIAS output is disabled, the output pin can be configured to be floating or to be actively

discharged. This is selected using the MICB1_DISCH and MICB2_DISCH register bits.

The MICBIAS generators can each operate as a voltage regulator or in bypass mode.

In Regulator mode, the output voltage is selected using the MICB1_LVL and MICB2_LVL register

bits.In this mode, AVDD1 must be at least 200mV greater than the required MICBIAS output

voltages.The MICBIAS outputs are powered from the AVDD1 supply pin, and use the internal

bandgap circuit as a reference.

Note that, in Regulator mode, the MICBIAS regulators are designed to operate without external

decoupling capacitors. It is important that parasitic capacitances on the MICBIAS1 or MICBIAS2 pins

do not exceed the specified limit in Regulator mode (see “Electrical Characteristics”).

In Bypass mode, the output pin (MICBIAS1 or MICBIAS2) is connected directly to AVDD1. This

enables a low power operating state. Note that, if a capacitive load is connected to MICBIAS1 or

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