PCM3168APAPR datasheet(56/66 Pages) TI1

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PCM3168A

SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016

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Layout Guidelines (continued)

12.1.6 VOUT1±, VOU2±, VOUT3±, VOUT4±, VOUT5±, VOUT6±, VOUT7±, and VOUT8± Pins

The differential to single-ended buffer with post LPF can be directly connected (without capacitors) to these

output pins (see Figure 62), thereby minimizing the use of coupling capacitors for the 2-VRMS outputs. The op

amp and resistors must be determined with consideration of degrading some performance through this

differential to single-ended and LPF buffer; there is about 1.5-dB degradation seen in the examples of Figure 61

and Figure 62.

12.1.7 MODE Pin

This pin is a logic input with quad-state input capability. The MODE pin is high when connected to VDD, low when

connected to DGND, and pulled up or pulled down through an external resistor and for the two mid-states in

order to distinguish the four input states. The pull-up or pull-down resistor must be 220 k

Ω, ±5% in tolerance.

Note that the state of the MODE pin is only sampled by a power-on or a low-to-high transition of the RST pin.

12.1.8 RST Pin

When the MODE pin setting changes to change the operating mode, the new mode setting does not take effect

immediately; a RST pin toggle is required to make the new mode setting valid, and for the new mode to take

effect.

12.1.9 OVF Pin

The OVF pin has two functions. It is primarily the flag for ADC overflow occurrence detection. It is also used to

indicate that the internal reset sequence is complete and that the device is ready to enter serial mode control.

12.1.10 System Clock and Audio Interface Clocks

The quality of SCKI may influence dynamic performance, because the PCM3168A device (both the ADC and

DAC) operates based on SCKI. Therefore, it may be required to consider the jitter, duty, and rise and fall time of

the system clock.

In slave mode, the PCM3168A device does not require a specific timing relationship between BCKAD/LRCKAD

and SCKI, and BCKDA/LRCKDA and SCKI; however, there is a possibility of performance degradation with a

certain timing relationship between them. In that case, specific timing relationship control might resolve this

performance degradation.

In master mode, there is a possibility of performance degradation because of heavy loads on BCKAD/LRCKAD,

BCKDA/LRCKDA, and DOUT1/2/3. It is recommended to load these pins as lightly as possible. Note that all

output clocks and signals go low; they do not go into a high-impedance state during power-save mode.

12.1.11 PowerPAD

The PowerPAD of the PCM3168A device is internally connected to the substrate of the silicon. It should be

connected to the ground plane with sufficient low conductance in electrical and thermal; see Figure 54. The

PowerPAD size is 7.25 mm x 7.00 mm (0.725 cm × 0.7 cm).

12.1.12 External Mute Control

For power-down ON/OFF control without the pop-noise that is generated by a DC level change on the DAC

output, the external mute control is generally required. Use of the following control sequence is recommended:

external mute ON, codec power-down ON, SCKI stop and resume if necessary, codec power-down OFF, and

external mute OFF control.

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