LAN9500AI datasheet(73/213 Pages) MICROCHIP

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DS00001875A-page 73

LAN950x

Special logic in the descrambler ensures synchronization with the remote PHY by searching for IDLE symbols within a

window of 4000 bytes (40us). This window ensures that a maximum packet size of 1514 bytes, allowed by the IEEE

802.3 standard, can be received with no interference. If no IDLE-symbols are detected within this time-period, receive

operation is aborted and the descrambler re-starts the synchronization process.

The descrambler can be bypassed by setting bit 0 of register 31.

5.6.2.5

Alignment

The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream Delimiter (SSD)

pair at the start of a packet. Once the code-word alignment is determined, it is stored and utilized until the next start of

frame.

5.6.2.6

5B/4B Decoding

The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The SSD, /J/K/, is translated

to “0101 0101” as the first 2 nibbles of the MAC preamble. Reception of the SSD causes the PHY to assert the internal

RX_DV signal, indicating that valid data is available on the Internal RXD bus. Successive valid code-groups are trans-

lated to data nibbles. Reception of either the End of Stream Delimiter (ESD) consisting of the /T/R/ symbols, or at least

two /I/ symbols causes the PHY to de-assert the internal carrier sense and RX_DV.

These symbols are not translated into data.

5.6.2.7

Receiver Errors

bit During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0

through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the internal MII’s RX_ER signal is asserted

and arbitrary data is driven onto the internal receive data bus (RXD) to the MAC. Should an error be detected during the

time that the /J/K/ delimiter is being decoded (bad SSD error), RX_ER is asserted and the value 1110b is driven onto

the internal receive data bus (RXD) to the MAC. Note that the internal MII’s data valid signal (RX_DV) is not yet asserted

when the bad SSD occurs.

5.6.3

10BASE-T TRANSMIT

Data to be transmitted comes from the MAC layer controller. The 10Base-T transmitter receives 4-bit nibbles from the

MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream. The data stream is then Manchester encoded

and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics.

The 10M transmitter uses the following blocks:

• MII (digital)

• TX 10M (digital)

• 10M Transmitter (analog)

• 10M PLL (analog)

5.6.3.1

10M Transmit Data Across the Internal MII Bus

The MAC controller drives the transmit data onto the internal TXD BUS. When the controller has driven TX_EN high to

indicate valid data, the data is latched by the MII block on the rising edge of TX_CLK. The data is in the form of 4-bit

wide 2.5MHz data.

5.6.3.2

Manchester Encoding

The 4-bit wide data is sent to the TX10M block. The nibbles are converted to a 10Mbps serial NRZI data stream. The

10M PLL locks onto the external clock or internal oscillator and produces a 20MHz clock. This is used to Manchester

encode the NRZ data stream. When no data is being transmitted (TX_EN is low), the TX10M block outputs Normal Link

Pulses (NLPs) to maintain communications with the remote link partner.

5.6.3.3

10M Transmit Drivers

The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered before being driven out

as a differential signal across the TXP and TXN outputs.

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