LAN9500AI datasheet(14/213 Pages) MICROCHIP

14 / 213 page

LAN950x

DS00001875A-page 14

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Transmit Data

(Internal PHY

Mode)

TXD3

IS/O8

(PU)

In internal PHY mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 122 for additional information.

Transmit Data

(External PHY

Mode)

TXD3

(PU)

In external PHY mode, this pin functions as the

transmit data 3 output to the external PHY.

General

Purpose I/O 7

(Internal PHY

Mode Only)

GPIO7

IS/O8/

OD8

(PU)

This General Purpose I/O pin is fully

programmable as either a push-pull output, an

open-drain output, or a Schmitt-triggered input.

Note:

(LAN9500A/LAN9500Ai ONLY):

GPIO7 may provide additional PHY Link

Up related functionality. Refer to Section

5.12.2.4, "Enabling PHY Link Up Wake

Events (LAN9500A/LAN9500Ai ONLY),"

on page 108 for additional information.

EEPROM Size

Configuration

Strap

EEP_SIZE

(PU)

The EEP_SIZE strap selects the size of the

EEPROM attached to the device.

0 = 128 byte EEPROM is attached and a total of

seven address bits are used.

1 = 256/512 byte EEPROM is attached and a total

of nine address bits are used.

Note:

A 3-wire style 1K/2K/4K EEPROM that is

organized for 128 x 8-bit or 256/512 x 8-

bit operation must be used.

See Note 3-1 for more information on configuration

straps.

Transmit Data

(Internal PHY

Mode)

TXD2

IS/O8

(PD)

In internal PHY mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 122 for additional information.

Transmit Data

(External PHY

Mode)

TXD2

(PD)

In external PHY mode, this pin functions as the

transmit data 2 output to the external PHY.

General

Purpose I/O 6

(Internal PHY

Mode Only)

GPIO6

IS/O8/

OD8

(PU)

This General Purpose I/O pin is fully

programmable as either a push-pull output, an

open-drain output, or a Schmitt-triggered input.

USB Port

Swap

Configuration

Strap

PORT_SWAP

(PD)

Swaps the mapping of USBDP and USBDM.

0 = USBDP maps to the USB D+ line and USBDM

maps to the USB D- line.

1 = USBDP maps to the USB D- line. USBDM

maps to the USB D+ line.

See Note 3-1 for more information on configuration

straps.

TABLE 3-1:

MII INTERFACE PINS (CONTINUED)

Num Pins

Name

Symbol

Buffer

Type

Description

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