LAN9500AI datasheet(81/213 Pages) MICROCHIP

81 / 213 page

 2010 - 2015 Microchip Technology Inc.

DS00001875A-page 81

LAN950x

TABLE 5-59:

GPIO PME FLAGS

Bits

Description

GPIO PME Enable

Setting this bit enables the assertion of the GPIO0 or GPIO8 pin, as a result of a Wakeup (GPIO) pin,

Magic Packet, or PHY Link Up. The host processor may use the GPIO0/GPIO8 pin to asynchronously

wake up, in a manner analogous to a PCI PME pin. GPIO0 signals the event when operating in Internal

PHY mode, while GPIO8 signals the event when operating in External PHY mode. Internal or External

PHY mode of operation is dictated by the PHY_SEL pin.

0 = The device does not support GPIO PME signaling.

1 = The device supports GPIO PME signaling.

Note:

When this bit is 0, the remaining GPIO PME parameters in this flag byte are ignored.

GPIO PME Configuration

This bit selects whether the GPIO PME is signaled on the GPIO pin as a level or a pulse. If pulse is

selected, the duration of the pulse is determined by the setting of the GPIO PME Length bit of this flag

byte. The level of the signal or the polarity of the pulse is determined by the GPIO PME Polarity bit of

this flag byte.

0 = GPIO PME is signaled via a level.

1 = GPIO PME is signaled via a pulse.

Note:

If GPIO PME Enable is 0, this bit is ignored.

GPIO PME Length

When the GPIO PME Configuration bit of this flag byte indicates that the GPIO PME is signaled by a

pulse on the GPIO pin, this bit determines the duration of the pulse.

0 = GPIO PME pulse length is 1.5 mS.

1 = GPIO PME pulse length is 150 mS.

Note:

If GPIO PME Enable is 0, this bit is ignored.

GPIO PME Polarity

Specifies the level of the signal or the polarity of the pulse used for GPIO PME signaling.

0 = GPIO PME signaling polarity is low.

1 = GPIO PME signaling polarity is high.

Note:

If GPIO PME Enable is 0, this bit is ignored.

GPIO PME Buffer Type

This bit selects the output buffer type for GPIO0/GPIO8.

0 = Open drain driver / open source

1 = Push-Pull driver

Note 1: Buffer Type = 0, Polarity = 0 implies Open Drain

Buffer Type = 0, Polarity = 1 implies Open Source

2: If GPIO PME Enable is 0, this bit is ignored.

GPIO PME WOL Select

Three types of wakeup events are supported; Magic Packet, PHY Link Up, and Wakeup Pin(s) assertion.

Wakeup Pin(s) are selected via the GPIO Wake 0-10 (GPIOWKn) field of the General Purpose IO Wake

Enable and Polarity Register (GPIO_WAKE). The Wakeup Enables are specified in bytes 1Eh and 1Fh

of the EEPROM. This bit selects whether Magic packet or Link Up wakeup events are supported.

0 = Magic packet wakeup supported.

1 = PHY linkup wakeup supported. (not supported in External PHY mode)

Note:

If GPIO PME Enable is 0, this bit is ignored.

GPIO10 Detection Select

This bit selects the detection mode for GPIO10 when operating in PME mode. In PME mode, GPIO10

is usable in both Internal and External PHY mode as a wakeup pin. This parameter defines whether the

wakeup should occur on an active high or active low signal.

0 = Active-low detection for GPIO10.

1 = Active-high detection for GPIO10.

Note:

If GPIO PME Enable is 0, this bit is ignored.

RESERVED

LAN9500AI Datasheet(PDF) 81 Page - Microchip Technology

LAN9500AI Datasheet(HTML) 81 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL