LAN9500AI datasheet(17/213 Pages) MICROCHIP

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 2010 - 2015 Microchip Technology Inc.

DS00001875A-page 17

LAN950x

TABLE 3-3:

JTAG PINS

Num Pins

Name

Symbol

Buffer

Type

Description

JTAG Test Port

Reset

(Internal PHY

Mode)

nTRST

(PU)

In internal PHY mode, this active-low pin functions

as the JTAG test port reset input.

Receive Data 0

(External PHY

Mode)

RXD0

(PD)

In external PHY mode, this pin functions as the

receive data 0 input from the external PHY.

JTAG Test

Data Out

(Internal PHY

Mode)

TDO

In internal PHY mode, this pin functions as the

JTAG data output.

PHY Reset

(External PHY

Mode)

nPHY_RST

In external PHY mode, this active-low pin functions

as the PHY reset output.

JTAG Test

Clock

(Internal PHY

Mode)

TCK

(PU)

In internal PHY mode, this pin functions as the

JTAG test clock. The maximum operating

frequency of this clock is 25MHz.

Receive Data 1

(External PHY

Mode)

RXD1

(PD)

In external PHY mode, this pin functions as the

receive data 1 input from the external PHY.

JTAG Test

Mode Select

(Internal PHY

Mode)

TMS

(PU)

In internal PHY mode, this pin functions as the

JTAG test mode select.

Receive Data 2

(External PHY

Mode)

RXD2

(PD)

In external PHY mode, this pin functions as the

receive data 2 input from the external PHY.

JTAG Test

Data Input

(Internal PHY

Mode)

TDI

(PU)

In internal PHY mode, this pin functions as the

JTAG data input.

Receive Data 3

(External PHY

Mode)

RXD3

(PD)

In external PHY mode, this pin functions as the

receive data 3 input from the external PHY.

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