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LAN9500AI Datasheet(PDF) 145 Page - Microchip Technology |
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LAN9500AI Datasheet(HTML) 145 Page - Microchip Technology |
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145 / 213 page  2010 - 2015 Microchip Technology Inc. DS00001875A-page 145 LAN950x 7.3.19 DATA PORT DATA 1 REGISTER (DP_DATA1) The Data Port Data register holds the write data for a write access and the resultant read data for a read access. Before reading the this register for the result of a read operation, the Data Port Ready bit should be checked. The Data Port Ready bit must indicate the data port is ready. Otherwise the read operation is still in progress. This register required when accessing the RX TLI and TX TLI RAMs. These RAMs have a width of 37 bits. Address: 050h Size: 32 bits Bits Description Type Default 31:5 RESERVED RO - 4:0 Data Port Data [36:32] R/W 00h |
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