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LAN9500AI Datasheet(PDF) 167 Page - Microchip Technology |
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LAN9500AI Datasheet(HTML) 167 Page - Microchip Technology |
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167 / 213 page  2010 - 2015 Microchip Technology Inc. DS00001875A-page 167 LAN950x 7.4.7 MII DATA REGISTER (MII_DATA) This register contains either the data to be written to the PHY register specified in the MII Access Register, or the read data from the PHY register whose index is specified in the MII Access Register. Refer toSection 7.4.6, "MII Access Reg- ister (MII_ACCESS)," on page 166 for further details. Address: 118h Size: 32 bits Note: The MIIBZY bit in the MII_ACCESS register must be cleared when writing to this register. Bits Description Type Default 31:16 RESERVED RO - 15:0 MII Data This contains the 16-bit value read from the PHY read operation or the 16- bit data value to be written to the PHY before an MII write operation. R/W 0000h |
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