PI7C8150BMA-33 datasheet(52/107 Pages) PERICOM

52 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 52 of 107

April 2015 – Revision 2.1



PI7C8150B asserts P_PERR_L two cycles following the data transfer, if the primary

interface parity error response bit is set in the command register.



PI7C8150B sets the detected parity error bit in the primary status register.



PI7C8150B sets the data parity detected bit in the primary status register, if the

primary interface parity-error-response bit is set in the command register.



PI7C8150B forwards the bad parity with the data back to the initiator on the secondary

bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the

secondary bus, the data is discarded and the data with bad parity is not returned to the

initiator.



PI7C8150B completes the transaction normally.

PI7C8150B returns to the initiator the data and parity that was received from the target.

When the initiator detects a parity error on this read data and is enabled to report it, the

initiator asserts PERR_L two cycles after the data transfer occurs. It is assumed that the

initiator takes responsibility for handling a parity error condition; therefore, when

PI7C8150B detects PERR_L asserted while returning read data to the initiator, PI7C8150B

does not take any further action and completes the transaction normally.

6.2.3

DELAYED WRITE TRANSACTIONS

When PI7C8150B detects a data parity error during a delayed write transaction, the

initiator drives data and data parity, and the target checks parity and conditionally asserts

PERR_L.

For delayed write transactions, a parity error can occur at the following times:



During the original delayed write request transaction



When the initiator repeats the delayed write request transaction



When PI7C8150B completes the delayed write transaction to the target

When a delayed write transaction is normally queued, the address, command, address

parity, data, byte enable bits, and data parity are all captured and a target retry is returned to

the initiator. When PI7C8150B detects a parity error on the write data for the initial

delayed write request transaction, the following events occur:



If the parity-error-response bit corresponding to the initiator bus is set, PI7C8150B

asserts TRDY_L to the initiator and the transaction is not queued. If multiple data

phases are requested, STOP_L is also asserted to cause a target disconnect. Two cycles

after the data transfer, PI7C8150B also asserts PERR_L.



If the parity-error-response bit is not set, PI7C8150B returns a target retry.

It queues the transaction as usual. PI7C8150B does not assert PERR_L.

In this case, the initiator repeats the transaction.



PI7C8150B sets the detected-parity-error bit in the status register corresponding to the

initiator bus, regardless of the state of the parity-error-response bit.

15-0048

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