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PI7C8150BMA-33 Datasheet(PDF) 56 Page - Pericom Semiconductor Corporation |
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PI7C8150BMA-33 Datasheet(HTML) 56 Page - Pericom Semiconductor Corporation |
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56 / 107 page  PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Page 56 of 107 April 2015 – Revision 2.1 Assertion of P_SERR_L is used to signal the parity error condition when the initiator does not know that the error occurred. Because the data has already been delivered with no errors, there is no other way to signal this information back to the initiator. If the parity error has forwarded from the initiating bus to the target bus, P_SERR_L will not be asserted. 6.3 DATA PARITY ERROR REPORTING SUMMARY In the previous sections, the responses of PI7C8150B to data parity errors are presented according to the type of transaction in progress. This section organizes the responses of PI7C8150B to data parity errors according to the status bits that PI7C8150B sets and the signals that it asserts. Table 6-1 shows setting the detected parity error bit in the status register, corresponding to the primary interface. This bit is set when PI7C8150B detects a parity error on the primary interface. Table 6-1. Setting the Primary Interface Detected Parity Error Bit Primary Detected Parity Error Bit Transaction Type Direction Bus Where Error Was Detected Primary/ Secondary Parity Error Response Bits 0 Read Downstream Primary x / x 0 Read Downstream Secondary x / x 1 Read Upstream Primary x / x 0 Read Upstream Secondary x / x 1 Posted Write Downstream Primary x / x 0 Posted Write Downstream Secondary x / x 0 Posted Write Upstream Primary x / x 0 Posted Write Upstream Secondary x / x 1 Delayed Write Downstream Primary x / x 0 Delayed Write Downstream Secondary x / x 0 Delayed Write Upstream Primary x / x 0 Delayed Write Upstream Secondary x / x X = don’t care Table 6-2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when PI7C8150B detects a parity error on the secondary interface. Table 6-2. Setting Secondary Interface Detected Parity Error Bit Secondary Detected Parity Error Bit Transaction Type Direction Bus Where Error Was Detected Primary/ Secondary Parity Error Response Bits 0 Read Downstream Primary x / x 1 Read Downstream Secondary x / x 0 Read Upstream Primary x / x 0 Read Upstream Secondary x / x 0 Posted Write Downstream Primary x / x 0 Posted Write Downstream Secondary x / x 0 Posted Write Upstream Primary x / x 1 Posted Write Upstream Secondary x / x 0 Delayed Write Downstream Primary x / x 0 Delayed Write Downstream Secondary x / x 0 Delayed Write Upstream Primary x / x 1 Delayed Write Upstream Secondary x / x X = don’t care 15-0048 |
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