PI7C8150BMA-33 datasheet(70/107 Pages) PERICOM

70 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 70 of 107

April 2015 – Revision 2.1

driven to a value of 1, the I/O enable, the memory enable, and the master enable bits are

internally masked to 0. This means that, as a target, PI7C8150B no longer accepts any I/O

or memory transactions, on either interface. When read, the register bits still reflect the

value originally written by a configuration write command; when GPIO[3] is deasserted,

the internal enable bits return to their original value (as they appear when read from the

command register). When this mode is enabled, as a master, PI7C8150B completes any

posted write or delayed request transactions that have already been queued.

Delayed completion transactions are not returned to the master in this mode because

PI7C8150B is not responding to any I/O or memory transactions during this time.

PI7C8150B continues to accept configuration transactions in live insertion mode. Once live

insertion mode brings PI7C8150B to a halt and queued transactions are completed, the

secondary reset bit in the bridge control register can be used to assert S_RST_L, if desired,

to reset and tri-state secondary bus devices, and to enable any live insertion hardware.

PCI POWER MANAGEMENT

PI7C8150B incorporates functionality that meets the requirements of the PCI Power

Management Specification, Revision 1.0. These features include:



PCI Power Management registers using the Enhanced Capabilities Port (ECP) address

mechanism



Support for D0, D3 hot and D3 cold power management states



Support for D0, D1, D2, D3 hot , and D3 cold power management states for devices

behind the bridge



Support of the B2 secondary bus power state when in the D3 hot power management

state

Table 11-1 shows the states and related actions that PI7C8150B performs during power

management transitions. (No other transactions are permitted.)

Table 11-1. Power Management Transitions

Current Status

Next State

Action

D3cold

Power has been removed from PI7C8150B. A power-up reset must

be performed to bring PI7C8150B to D0.

D3hot

If enabled to do so by the BPCCE pin, PI7C8150B will disable the

secondary clocks and drive them LOW.

Unimplemented power state. PI7C8150B will ignore the write to the

power state bits (power state remains at D0).

Unimplemented power state. PI7C8150B will ignore the write to the

power state bits (power state remains at D0).

D3hot

PI7C8150B enables secondary clock outputs and performs an internal

chip reset. Signal S_RST_L will not be asserted. All registers will

be returned to the reset values and buffers will be cleared.

D3hot

D3cold

Power has been removed from PI7C8150B. A power-up reset must

be performed to bring PI7C8150B to D0.

D3cold

Power-up reset. PI7C8150B performs the standard power-up reset

functions as described in Section 12.

PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME#

signals do not pass through PCI-to-PCI bridges.

15-0048

PI7C8150BMA-33 Datasheet(PDF) 70 Page - Pericom Semiconductor Corporation

PI7C8150BMA-33 Datasheet(HTML) 70 Page - Pericom Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL