PI7C8150BMA-33 datasheet(82/107 Pages) PERICOM

82 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 82 of 107

April 2015 – Revision 2.1

Bit

Function

Type

Description

VGA enable

R/W

Controls the bridge’s response to VGA compatible addresses.

0: does not forward VGA compatible memory and I/O addresses

from primary to secondary

1: forward VGA compatible memory and I/O addresses from primary

to secondary regardless of other settings

Reset to 0

Reserved

R/O

Reserved. Returns 0 when read.

Master Abort

Mode

R/W

Control’s bridge’s behavior responding to master aborts on

secondary interface.

0: does not report master aborts (returns FFFF_FFFFh on reads and

discards data on writes)

1: reports master aborts by signaling target abort if possible by the

assertion of P_SERR_L if enabled

Reset to 0

Secondary

Interface Reset

R/W

Controls the assertion of S_RESET_L signal pin on the secondary

interface

0: does not force the assertion of S_RESET_L pin

1: forces the assertion of S_RESET_L

Reset to 0

Fast Back-to-

Back Enable

R/W

Controls bridge’s ability to generate fast back-to-back transactions to

different devices on the secondary interface.

0: does not allow fast back-to-back transactions

1: enables fast back-to-back transactions

Reset to 0

Primary Master

Timeout

R/W

Set’s the maximum number of PCI clocks the bridge will wait for an

initiator on the primary to repeat a delayed transaction request. The

counter starts right after the delayed transaction is at the front of the

queue. If the master has not repeated at least once before the counter

expires, the bridge discards the transaction from the queue.

0: 2

PCI clocks

1: 2

PCI clocks

Reset to 0

Secondary

Master Timeout

R/W

Set’s the maximum number of PCI clocks the bridge will wait for an

initiator on the secondary to repeat a delayed transaction request. The

counter starts right after the delayed transaction is at the front of the

queue. If the master has not repeated at least once before the counter

expires, the bridge discards the transaction from the queue.

0: 2

PCI clocks

1: 2

PCI clocks

Reset to 0

Master Timeout

Status

R/WC

This bit is set to 1 when either the primary master timeout counter or

secondary master timeout counter expires.

Reset to 0

Discard Timer

P_SERR_L

enable

R/W

This bit is set to 1 and P_SERR_L is asserted when either the

primary discard timer or the secondary discard timer expire.

Reset to 0

31-28

Reserved

R/O

Reserved. Returns 0 when read.

15-0048

PI7C8150BMA-33 Datasheet(PDF) 82 Page - Pericom Semiconductor Corporation

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