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PI7C8150BMA-33 Datasheet(PDF) 92 Page - Pericom Semiconductor Corporation

Part # PI7C8150BMA-33
Description  ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PDF  107 Pages
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Manufacturer  PERICOM [Pericom Semiconductor Corporation]
Direct Link  http://www.pericom.com
Logo PERICOM - Pericom Semiconductor Corporation

PI7C8150BMA-33 Datasheet(HTML) 92 Page - Pericom Semiconductor Corporation

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PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Page 92 of 107
April 2015 – Revision 2.1
14.1.50
CAPABILITY ID REGISTER – OFFSET DCh
Bit
Function
Type
Description
7:0
Enhanced
Capabilities ID
R/O
Read as 01h to indicate that these are power management enhanced
capability registers.
14.1.51
NEXT ITEM POINTER REGISTER – OFFSET DCh
Bit
Function
Type
Description
15:8
Next Item
Pointer
R/O
Points to slot number register (B0h).
14.1.52
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET
DCh
Bit
Function
Type
Description
18:16
Power
Management
Revision
R/O
Read as 001 to indicate the device is compliant to Revision 1.0 of
PCI Power Management Interface Specifications.
19
PME# Clock
R/O
Read as 0 to indicate PI7C8150B does not support the PME# pin.
20
Auxiliary Power
R/O
Read as 0 to indicate PI7C8150B does not support the PME# pin or
an auxiliary power source.
21
Device Specific
Initialization
R/O
Read as 0 to indicate PI7C8150B does not have device specific
initialization requirements.
24:22
Reserved
R/O
Read as 0
25
D1 Power State
Support
R/O
Read as 0 to indicate PI7C8150B does not support the D1 power
management state.
26
D2 Power State
Support
R/O
Read as 0 to indicate PI7C8150B does not support the D2 power
management state.
31:27
PME# Support
R/O
Read as 0 to indicate PI7C8150B does not support the PME# pin.
14.1.53
POWER MANAGEMENT DATA REGISTER – OFFSET E0h
Bit
Function
Type
Description
1:0
Power State
R/W
Indicates the current power state of PI7C8150B. If an
unimplemented power state is written to this register, PI7C8150B
completes the write transaction, ignores the write data, and does not
change the value of the field. Writing a value of D0 when the
previous state was D3 cause a chip reset without asserting
S_RESET_L
00: D0 state
01: not implemented
10: not implemented
11: D3 state
Reset to 0
7:2
Reserved
R/O
Read as 0
8
PME# Enable
R/O
Read as 0 as PI7C8150B does not support the PME# pin.
12:9
Data Select
R/O
Read as 0 as the data register is not implemented.
14:13
Data Scale
R/O
Read as 0 as the data register is not implemented.
15
PME status
R/O
Read as 0 as the PME# pin is not implemented.
15-0048



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