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PI7C8150BMA-33 Datasheet(PDF) 84 Page - Pericom Semiconductor Corporation

Part # PI7C8150BMA-33
Description  ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PDF  107 Pages
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Manufacturer  PERICOM [Pericom Semiconductor Corporation]
Direct Link  http://www.pericom.com
Logo PERICOM - Pericom Semiconductor Corporation

PI7C8150BMA-33 Datasheet(HTML) 84 Page - Pericom Semiconductor Corporation

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PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Page 84 of 107
April 2015 – Revision 2.1
14.1.30
ARBITER CONTROL REGISTER – OFFSET 40h
Bit
Function
Type
Description
24:16
Arbiter Control
R/W
Each bit controls whether a secondary bus master is assigned to the
high priority group or the low priority group.
Bits [24:16] correspond to request inputs S_REQ_L[8:0]
respectively.
Bit 24 corresponds to S_REQ_L[8]
Bit 16 corresponds to S_REQ_L[0]
0: low priority
1: high priority
Reset to 0
25
Priority of
Secondary
Interface
R/W
Controls whether the secondary interface of the bridge is in the high
priority group or the low priority group.
0: low priority
1: high priority
Reset to 0
31:26
Reserved
R/O
Reserved. Returns 0 when read.
14.1.31
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h
Bit
Function
Type
Description
0
Memory Read
Flow Through
Enable
R/W
Controls ability to do memory read flow through
0: Disable flow through during a memory read transaction
1: Enable flow through during a memory read transaction
Reset to 0
1
Park
R/W
Controls bus arbiter’s park function
0: Park to last master
1: Park to bridge
Reset to 0
2
Downstream
Dynamic
Prefetch Control
R/W
Controls the downstream (P to S) memory read line and memory read
multiple prefetching dynamic control
0: Enable the downstream memory read line and memory read
multiple prefetching dynamic control
1: Disable the downstream memory read line and memory read
multiple prefetching dynamic control
Reset to 0
3
Upstream
Dynamic
Prefetch Control
R/W
Controls the upstream (S to P) memory read line and memory read
multiple prefetching dynamic control
0: Enable the upstream memory read line and memory read multiple
prefetching dynamic control
1: Disable the upstream memory read line and memory read multiple
prefetching dynamic control
Reset to 0
15:4
Reserved
R/O
Reserved. Returns 0 when read.
15-0048



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