PI7C8150BMA-33 datasheet(66/107 Pages) PERICOM

66 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 66 of 107

April 2015 – Revision 2.1

the bus is idle, its bus grant is asserted, and the device’s request is not asserted. The AD

and CBE signals should be driven first, with the PAR signal driven one cycle later.

PI7C8150B parks the primary bus only when P_GNT_L is asserted, P_REQ_L is de-

asserted, and the primary PCI bus is idle. When P_GNT_L is de-asserted, PI7C8150B 3-

states the P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle. If PI7C8150B is

parking the primary PCI bus and wants to initiate a transaction on that bus, then

PI7C8150B can start the transaction on the next PCI clock cycle by asserting P_FRAME_L

if P_GNT_L is still asserted.

If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the

last master that used the PCI bus. That is, PI7C8150B keeps the secondary bus grant

asserted to a particular master until a new secondary bus request comes along. After reset,

PI7C8150B parks the secondary bus at itself until transactions start occurring on the

secondary bus. Offset 48h, bit 1, can be set to 1 to park the secondary bus at PI7C8150B.

By default, offset 48h, bit 1, is set to 0. If the internal arbiter is disabled, PI7C8150B parks

the secondary bus only when the reconfigured grant signal, S_REQ_L[0], is asserted and

the secondary bus is idle.

CLOCKS

This chapter provides information about the clocks.

9.1

PRIMARY CLOCK INPUTS

PI7C8150B implements a primary clock input for the PCI interface. The primary interface

is synchronized to the primary clock input, P_CLK, and the secondary interface is

synchronized to the secondary clock. In synchronous mode, the secondary clock is derived

internally from the primary clock, P_CLK. PI7C8150B operates at a maximum frequency

of 66 MHz (33MHz for PI7C8150B-33).

9.2

SECONDARY CLOCK OUTPUTS

PI7C8150B has 10 secondary clock outputs, S_CLKOUT[9:0] that can be used as clock

inputs for up to nine external secondary bus devices. In synchronous mode, the

S_CLKOUT[9:0] outputs are derived from P_CLK. The secondary clock edges are delayed

from P_CLK edges by a minimum of 0ns. This is the rule for using secondary clocks:

Each secondary clock output is limited to no more than one load.

9.3

ASYNCHRONOUS MODE

In asynchronous mode, the PI7C8150B can be run in the following frequency configuration:

Primary (MHz)

Secondary (MHz)

25MHz to 66MHz

PI7C8150B-33 can be run in the following frequency configuration:

15-0048

PI7C8150BMA-33 Datasheet(PDF) 66 Page - Pericom Semiconductor Corporation

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