PI7C8150BMA-33 datasheet(9/107 Pages) PERICOM

9 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 9 of 107

April 2015 – Revision 2.1

LIST OF TABLES

TABLE 2-1. PIN LIST – 208-PIN FQFP............................................................................................................18

TABLE 2-2. PIN LIST – 256-PIN PBGA...........................................................................................................20

TABLE 3-1. PCI TRANSACTIONS.....................................................................................................................22

TABLE 3-2. WRITE TRANSACTION FORWARDING ..........................................................................................23

TABLE 3-3. WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES ......................................................26

TABLE 3-4. READ PREFETCH ADDRESS BOUNDARIES....................................................................................28

TABLE 3-5. READ TRANSACTION PREFETCHING............................................................................................28

TABLE 3-6. DEVICE NUMBER TO IDSEL S_AD PIN MAPPING ......................................................................32

TABLE 3-7. DELAYED WRITE TARGET TERMINATION RESPONSE ..................................................................36

TABLE 3-8. RESPONSE TO POSTED WRITE TARGET TERMINATION ................................................................37

TABLE 3-9. RESPONSE TO DELAYED READ TARGET TERMINATION...............................................................38

TABLE 5-1. SUMMARY OF TRANSACTION ORDERING ....................................................................................48

TABLE 6-1. SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT............................................56

TABLE 6-2. SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT..............................................56

TABLE 6-3. SETTING PRIMARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT ..........................57

TABLE 6-4. SETTING SECONDARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT .....................57

TABLE 6-5. ASSERTION OF P_PERR_L .........................................................................................................58

TABLE 6-6. ASSERTION OF S_PERR_L .........................................................................................................58

TABLE 6-7. ASSERTION OF P_SERR_L FOR DATA PARITY ERRORS..............................................................59

TABLE 10-1. GPIO OPERATION.....................................................................................................................68

TABLE 10-2. GPIO SERIAL DATA FORMAT ...................................................................................................69

TABLE 11-1. POWER MANAGEMENT TRANSITIONS .......................................................................................70

TABLE 16-1. TAP PINS ..................................................................................................................................97

TABLE 16-2. JTAG BOUNDARY REGISTER ORDER........................................................................................99

LIST OF FIGURES

FIGURE 8-1

SECONDARY ARBITER EXAMPLE..............................................................................................64

FIGURE 16-1

TEST ACCESS PORT BLOCK DIAGRAM ...................................................................................96

FIGURE 17-1

PCI SIGNAL TIMING MEASUREMENT CONDITIONS...............................................................103

FIGURE 18-1

208-PIN FQFP PACKAGE OUTLINE .......................................................................................105

FIGURE 18-2

256-PIN PBGA PACKAGE OUTLINE......................................................................................106

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PI7C8150BMA-33 Datasheet(PDF) 9 Page - Pericom Semiconductor Corporation

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