PI7C8150BMA-33 datasheet(103/107 Pages) PERICOM

103 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 103 of 107

April 2015 – Revision 2.1

17.3

AC SPECIFICATIONS

Figure 17-1

PCI Signal Timing Measurement Conditions

66 MHz

33 MHz

Symbol

Parameter

Min.

Max.

Min.

Max.

Units

Tsu

Input setup time to CLK – bused signals

1,2,3

Tsu(ptp)

Input setup time to CLK – point-to-point

1,2,3

10, 12

Input signal hold time from CLK

1,2

Tval

CLK to signal valid delay – bused signals

1,2,3

Tval(ptp)

CLK to signal valid delay – point-to-point

1,2,3

Ton

Float to active delay

1,2

Toff

Active to float delay

1,2

1. See Figure 17-1 PCI Signal Timing Measurement Conditions.

2. All primary interface signals are synchronized to P_CLK. All secondary interface

signals are synchronized to S_CLKOUT.

3. Point-to-point signals are P_REQ_L, S_REQ_L[7:0], P_GNT_L, S_GNT_L[7:0],

HSLED, HS_SW_L, HS_EN, and ENUM_L. Bused signals are P_AD, P_BDE_L, P_PAR,

P_PERR_L, P_SERR_L, P_FRAME_L, P_IRDY_L, P_TRDY_L, P_LOCK_L,

P_DEVSEL_L, P_STOP_L, P_IDSEL, S_AD, S_CBE_L, S_PAR, S_PERR_L,

S_SERR_L, S_FRAME_L, S_IRDY_L, S_TRDY_L, S_LOCK_L, S_DEVSEL_L, and

S_STOP_L.

4. REQ_L signals have a setup of 12 and GNT_L signals have a setup of 10.

17.4

66MHZ TIMING

Symbol

Parameter

Condition

Min.

Max.

Units

TSKEW

SKEW among S_CLKOUT[9:0]

0.250

TDELAY

DELAY between PCLK and S_CLKOUT[9:0]

20pF load

3.14

5.07

TCYCLE

P_CLK, S_CLKOUT[9:0] cycle time

THIGH

P_CLK, S_CLKOUT[9:0] HIGH time

TLOW

P_CLK, S_CLKOUT[9:0] LOW time

17.5

33MHZ TIMING

15-0048

PI7C8150BMA-33 Datasheet(PDF) 103 Page - Pericom Semiconductor Corporation

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