CP3SP33SMSSLASHNOPB datasheet(163/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

ERROR

The Error bit is set when three attempts have been made to receive a packet and no

packet has been received. Software clears the ERROR bit to detect the next error

event. An interrupt is asserted when the bit is set. This bit is only valid for Bulk and

Interrupt endpoints.

0 – No error event detected since the bit was last cleared.

1 – Error event detected.

DATAERROR

The DATAERROR bit (Isochronous endpoint only) is set when the RXPKTRDY bit is

set and the data packet has a CRC or bit-stuffing error. It is clear when the

RXPKTRDY bit is clear.

0 – No data error since the bit was last cleared.

1 – Data error detected.

NAKTIMEOUT

The NAKTIMEOUT bit (Bulk endpoint only) is set when the receive endpoint is

halted following receipt of NAK responses for longer than the time set as the NAK

limit in the RXINTERVAL register. Software should clear this bit to allow the endpoint

to continue.

0 – No timeout.

1 – NAK timeout occurred.

FLUSHFIFO

The FLUSHFIFO bit is written with 1 to flush the receive FIFO. The FIFO pointer is

reset and the RXPKTRDY bit is cleared. The FLUSHFIFO bit has no effect unless

RXPKTRDY bit is set. If double-buffering is enabled, the FLUSHFIFO bit may need

to be written twice to completely clear the FIFO.

0 – Normal operation.

1 – Flush the receive FIFO and clear the RXPKTRDY bit.

REQPKT

The Request Packet bit is written with 1 to request an IN transaction. The REQPKT

bit is cleared when the RXPKTRDY bit is set.

0 – No request asserted.

1 – Request for an IN transaction asserted.

RXSTALL

The Receive STALL Handshake bit is set when a STALL handshake is received.

Software clears the RXSTALL bit to detect the next STALL handshake. An interrupt

is asserted (if enabled) when this bit is set.

0 – No STALL handshake detected since the bit was last cleared.

1 – STALL handshake detected.

CLRDATATOG

The Clear Data Toggle bit is written with 1 to reset the endpoint data toggle to 0.

0 – Normal operation.

1 – Write 1 to reset endpoint data toggle to 0.

AUTOREQ

The Automatic Request bit specifies whether the REQPKT bit is automatically set

when the RXPKTRDY bit is cleared.

0 – Automatic request is disabled.

1 – Automatic request is enabled.

AUTOCLEAR

The Automatic Clear bit is set by software to enable a mode in which the

RXPKTRDY bit is automatically cleared when data of the maximum packet size

(value in RXMAXP register) is unloaded from the receive FIFO. If a packet of less

than the maximum packet size is unloaded, then the RXPKTRDY bit must be set

explicitly by software.

0 – Normal mode.

1 – Automatically clear RXPKTRDY when maximum packet size packet is unloaded

from the receive FIFO.

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