CP3SP33SMSSLASHNOPB datasheet(193/407 Pages) TI1

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CICLR

CIPND

Clear interrupt flags of every

message buffer individually

ICODE

CIEN

CICEN

IRQ

IST3

IST2

IST1

IST0

DS043

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

•

CAN error conditions

–

Detection of an CAN error. (The CEIPND bit in the CIPND register will be set as well as the

corresponding bits in the error diagnostic register CEDIAG.)

The receive/transmit interrupt access to every message buffer can be individually enabled/disabled in the

CIEN register. The pending flags of the message buffer are located in the CIPND register (read only) and

can be cleared by resetting the flags in the CICLR registers.

22.7.1 Highest Priority Interrupt Code

To reduce the decoding time for the CIPND register, the buffer interrupt request with the highest priority is

placed as interrupt status code into the IST[3:0] section of the CSTPND register.

Each of the buffer interrupts as well as the error interrupt can be individually enabled or disabled in the

CAN Interrupt Enable register (CIEN). As soon as an interrupt condition occurs, every interrupt request is

indicated by a flag in the CAN Interrupt Pending register (CIPND). When the interrupt code logic for the

present highest priority interrupt request is enabled, this interrupt will be translated into the IST3:0 bits of

the CAN Status Pending register (CSTPND). An interrupt request can be cleared by setting the

corresponding bit in the CAN Interrupt Clear register (CICLR).

Figure 22-26 shows the CAN interrupt management.

Figure 22-26. Interrupt Management

The highest priority interrupt source is translated into the bits IRQ and IST3:0 as shown in Table 22-5.

Table 22-5. Highest Priority Interrupt Code (ICEN=FFFF)

CAN INTERRUPT REQUEST

IRQ

IST3

IST2

IST1

IST0

No Request

Error Interrupt

Buffer 0

Buffer 1

Buffer 2

Buffer 3

Buffer 4

Buffer 5

Buffer 6

Buffer 7

Buffer 8

Dual CAN Interfaces

193

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