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CP3SP33SMS/NOPB Datasheet(PDF) 195 Page - Texas Instruments |
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CP3SP33SMS/NOPB Datasheet(HTML) 195 Page - Texas Instruments |
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195 / 407 page  CP3SP33 www.ti.com SNOSCW5 – MAY 2013 If a buffer is busy during the reception of an object (copy process from the hidden receive buffer) or is scheduled for transmission, the CPU has no write access to the data contents of the buffer. Write to the status/control byte and read access to the whole buffer is always enabled. All configuration and status registers can either be accessed by the CAN module or the CPU. These registers provide single-cycle access without any potential wait state. All register descriptions within the next sections have the following layout: 15 0 Bit/Field Names Reset Value CPU Access (R = read only, W = write only, R/W = read/write) The CAN peripheral registers and shared memory are implemented as 16-bit words which occupy the lower half of 32-bit doubleword locations in the address space. The upper half is reserved. 22.9.2 Message Buffer Organization The message buffers are the communication interfaces between CAN and the CPU for the transmission and the reception of CAN frames. There are 15 message buffers located at fixed addresses in RAM. As shown in Table 22-6, each buffer consists of two words reserved for the identifiers, 4 words reserved for up to eight CAN data bytes, one word reserved for the time stamp, and one word for data length code, transmit priority code, and the buffer status codes. Table 22-6. Message Buffer Map Buffer Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register BASE + 00h CNSTAT DLC Reserved PRI ST BASE + 04h TSTP TSTP[15:0] BASE + 08h DATA3 Data7[7:0] Data8[7:0] BASE + 0Ch DATA2 Data5[7:0] Data6[7:0] BASE + 10h DATA1 Data3[7:0] Data4[7:0] BASE + 14h DATA0 Data1[7:0] Data2[7:0] BASE + 18h ID0 XI[14:0] RTR BASE + 1Ch ID1 XI[28:18]/ID[10:0] SRR/RTR IDE XI[17:15] 22.10 CAN Controller Registers Table 22-7 lists the registers for the two CAN modules (CAN0 and CAN1). Table 22-7. CAN Controller Registers NAME ADDRESS DESCRIPTION CNSTAT See Table 22-6 Message Buffer Status/Control Register CGCR0 FF BA00h CAN0 Global Configuration Register CGCR1 FF BE00h CAN1 Global Configuration Register CTIM0 FF BA04h CAN0 Timing Register CTIM1 FF BE04h CAN1 Timing Register GMSKX0 FF BA08h CAN0 Global Mask Register GMSKX1 FF BE08h CAN1 Global Mask Register GMSKB0 FF BA0Ch CAN0 Global Mask Register GMSKB1 FF BE0Ch CAN1 Global Mask Register BMSKX0 FF BA10h CAN0 Basic Mask Register Copyright © 2013, Texas Instruments Incorporated Dual CAN Interfaces 195 Submit Documentation Feedback Product Folder Links :CP3SP33 |
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