TMS320DM814X datasheet(185/376 Pages) TI1

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TMS320DM8148, TMS320DM8147

www.ti.com

SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

7.2.7

Standby Mode

The device supports Low-Power Standby Mode as described below.

Standby Mode is defined as a state in which:

•

All switchable power domains are in "OFF" state

•

The ARM Cortex-A8 is executing an IDLE loop at its lowest frequency of operation

•

All functional blocks not needed for a given application are clock gated

For detailed instructions on entering and exiting from Standby Mode see the Power, Reset, and Clock

Management (PRCM) Module chapter of the TMS320DM814x DaVinci Digital Media Processors Technical

Reference Manual (Literature Number: SPRUGZ8).

7.2.8

Supply Sequencing

The device power supplies are organized into four Supply Sequencing Groups:

1. All CVDD supplies (CVDD, CVDD_x)

2. All 1.5-/1.8-V DVDD_DDR[x] Supplies (1.5 V for DDR3, 1.8 V for DDR2)

3. All 1.8-V Supplies (DVDD_x, DVDD_M, VDDA_x_1P8, VDDA_1P8)

4. All 3.3-V Supplies (DVDD, DVDD_x, DVDD_C, VDDA_x_3P3)

To ensure proper device operation, a specific power-up and power-down sequence must be followed.

Some TI power-supply devices include features that facilitate these power sequencing requirements — for

example, TI’s TPS659113 integrated PMIC. For more information on TI power supplies and their features,

visit www.ti.com/processorpower.

For more detailed information on the actual power supply names and their descriptions, see Table 3-49,

Supply Voltages Terminal Functions.

7.2.8.1

Power-Up Sequence

For proper device operation, the following power-up sequence in Table 7-6 and must be followed.

Table 7-6. Power-Up Sequence Ramping Values

NO.

DESCRIPTION

MIN

MAX

UNIT

1.8 V and DVDD_DDR[x] supplies stable to 3.3 V supplies

ramp start

1.8 V supplies to 1.5-/1.8- V DVDD_DDR[x] supplies

0(1)

1.8 V supplies stable to CVDD, CVDD_x variable supplies

0(1)

ramp start

CVDD variable supply ramp start to CVDD_x variable

supplies ramp start

Master

All supplies valid to power-on-reset (POR high)

4 096

Clocks

(1)

The 1.8 V supplies must be

≥ 1.5-/1.8-V DVDD_DDR[x] supplies.

Power, Reset, Clocking, and Interrupts

185

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