M38B53M4-059FP datasheet(118/355 Pages) MITSUBISHI

118 / 355 page

2-30

38B5 Group User’s Manual

APPLICATION

2.2 Timer

Fig. 2.2.27 Control procedure

RESET

SEI

P6D

TXM1

TXM2

TXL

TXH

INTEDGE

T12M

ICON1

CLI

1011X1002

XXXXXX002

FF16

0X10XX1X2

XXXX1X1X2

RTI

(address 0D16),bit1

(address 2E16)

(address 2F16)

(address 2C16)

(address 2D16)

(address 3A16),bit6

(address 2816)

(address 2116)

(address 3E16)

TXM1

T12M

(address 2E16),bit7

(address 2816),bit1

q X: This bit is not used here. Set it to “0” or “1” arbitrary.

•All interrupts disabled

Initialization

•Setting P61/CNTR0/CNTR2 pin to input mode

•Timer X: Pulse width measurement mode

(Measuring “H” pulse width of input pulses from CNTR2 pin)

•Setting Timer X count value

•CNTR0 pin edge: Falling edge count

•External pulses input from CNTR0 pin selected as Timer 2’s count source

•Setting “0” to Timer 2

•Timers X and 2 interrupts: Enabled

•Timers X and 2 count start

•Interrupts enabled

Timer X interrupt process routine (Note 1)

CLT (Note 2)

CLD (Note 3)

Push registers to stack

Error processing

Pop registers

Notes1: Timer X interrupt also occurs owing to factors other than

measurement level.(CNTR2 input = “L” in this application)

Process it by software as error proccesing is performed for

measurement level as necessary . CNTR2 input level can be

checked by reading the contents of sharing port P61 register.

2: When using Index X mode flag (T)

3: When using Decimal mode flag (D)

•Popping registers pushed to stack

•Pushing registers used in interrupt process routine

M38B53M4-059FP Datasheet(PDF) 118 Page - Mitsubishi Electric Semiconductor

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