TMS320DM814X datasheet(201/377 Pages) TI1

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AUXOSC_MXI/

AUX_CLKIN

AUXOSC_MXO

VSSA_AUXOSC

DEVOSC_MXI/

DEV_CLKIN

DEVOSC_MXO

VSSA_DEVOSC

TMS320DM8148, TMS320DM8147

www.ti.com

SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

7.4.1.2

Using a 1.8V LVCMOS-Compatible Clock Input

A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillators as the DEV and

AUX clock inputs to the system. The external connections to support this are shown in Figure 7-9 and

Figure 7-10. The DEV_CLKIN and AUX_CLKIN pins are connected to the 1.8-V LVCMOS-Compatible

clock sources. The DEV_MXO and AUX_MXO pins are left unconnected. The VSSA_DEVOSC and

VSSA_AUXOSC pins are connected to board ground (VSS).

Figure 7-9. 1.8-V LVCMOS-Compatible Clock Input (DEV_OSC)

Figure 7-10. 1.8-V LVCMOS-Compatible Clock Input (AUX_OSC)

The clock source must meet the DEVOSC_MXI/DEV_CLKIN timing requirements shown in Table 7-15,

Timing Requirements for DEVOSC_MXI/DEV_CLKIN.

The clock source must meet the AUXOSC_MXI/AUX_CLKIN timing requirements shown in Table 7-16,

Timing Requirements for AUXOSC_MXI/AUX_CLKIN.

7.4.2

SERDES_CLKN/P Input Clock

A high-quality, low-jitter differential clock source is required for the PCIE PHY and is an optional clock

source for the SATA PHY. The clock is required to be AC coupled to the SERDES_CLKP and

SERDES_CLKN device pins according to the specifications in Table 7-13. Both the clock source and the

coupling capacitors should be placed physically as close to the processor as possible. In addition, make

sure to follow any PCB routing and termination recommendations that the clock source manufacturer

recommends.

Table 7-13. SERDES_CLKN/P AC Coupling Capacitors Recommendations

PARAMETER

MIN

TYP

MAX

UNIT

SERDES_CLKN/P AC coupling capacitor value

0.24

0.27

1.0

Power, Reset, Clocking, and Interrupts

201

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