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TMS320DM814X Datasheet(PDF) 286 Page - Texas Instruments |
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TMS320DM814X Datasheet(HTML) 286 Page - Texas Instruments |
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286 / 377 page  Data/Control input Data/Control output 6 7 5 2 1 PCLK (positive edge clocking) PCLK (negative edge clocking) 4 3 4 TMS320DM8148, TMS320DM8147 SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 www.ti.com Table 8-49. Switching Characteristics Over Recommended Operating Conditions for ISSCAM (see Figure 8-45) OPP100/120/166 NO. PARAMETER UNIT MIN MAX 15 td(PCLK-FLD) Delay time, PCLK rising/falling clock edge to Control valid 3 11.5 ns 16 td(PCLK-VS) Delay time, PCLK rising/falling clock edge to Control valid 3 11.5 ns 17 td(PCLK-HS) Delay time, PCLK rising/falling clock edge to Control valid 3 11.5 ns 18 td(PCLK-STROBE) Delay time, PCLK rising/falling clock edge to Control valid 3 11.5 ns 19 td(PCLK-SHUTTER) Delay time, PCLK rising/falling clock edge to Control valid 3 11.5 ns Figure 8-45. ISSCAM Timings 286 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320DM8148 TMS320DM8147 |
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