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TMS320DM814X Datasheet(PDF) 317 Page - Texas Instruments |
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TMS320DM814X Datasheet(HTML) 317 Page - Texas Instruments |
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317 / 377 page  A1 A2 Processor Differential Clock Output Buffer DDR Differential CK Input Buffer Routed as Differential Pair AT Rcp Clock Parallel Terminator A1 A2 AT Rcp Cac DDR_1V5 0.1 µF + – + – = Rtt A2 A3 AT Vtt TMS320DM8148, TMS320DM8147 www.ti.com SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 Figure 8-69. ADDR_CTRL Routing for Two Mirrored DDR3 Devices 8.13.4.2.4.11.7 One DDR3 Device A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as one bank (CS), 16-bits wide. 8.13.4.2.4.11.8 CK and ADDR_CTRL Topologies, One DDR3 Device Figure 8-70 shows the topology of the CK net classes and Figure 8-71 shows the topology for the corresponding ADDR_CTRL net classes. Figure 8-70. CK Topology for One DDR3 Device Copyright © 2011–2013, Texas Instruments Incorporated Peripheral Information and Timings 317 Submit Documentation Feedback Product Folder Links: TMS320DM8148 TMS320DM8147 |
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