TMS320DM814X datasheet(319/377 Pages) TI1

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Processor

DQ and DM

IO Buffer

DDR

DQ and DM

IO Buffer

n = 0, 1, 2, 3

Processor

DQS

IO Buffer

DDR

DQS

IO Buffer

Routed Differentially

n = 0, 1, 2, 3

DQSn-

DQSn+

Rtt

Vtt

TMS320DM8148, TMS320DM8147

www.ti.com

SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

Figure 8-73. ADDR_CTRL Routing for One DDR3 Device

8.13.4.2.4.12 Data Topologies and Routing Definition

No matter the number of DDR3 devices used, the data line topology is always point-to-point, so its

definition is simple.

Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is

better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure

there are nearby ground vias to allow the return currents to transition between reference planes if both

reference planes are ground or DVDD_DDR. Ensure there are nearby bypass capacitors to allow the

return currents to transition between reference planes if one of the reference planes is ground. The goal is

to minimize the size of the return current loops.

8.13.4.2.4.12.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices

DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. Figure 8-74

and Figure 8-75 show these topologies.

Figure 8-74. DQS Topology

Figure 8-75. DQ/DM Topology

8.13.4.2.4.12.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices

Figure 8-76 and Figure 8-77 show the DQS and DQ/DM routing.

Peripheral Information and Timings

319

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TMS320DM814X Datasheet(PDF) 319 Page - Texas Instruments

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