TMS320DM814X datasheet(320/377 Pages) TI1

320 / 377 page

n = 0, 1, 2, 3

DQ and DM

DQSn+

DQSn-

n = 0, 1, 2, 3

Routed Differentially

DQS

TMS320DM8148, TMS320DM8147

SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

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Figure 8-76. DQS Routing With Any Number of Allowed DDR3 Devices

Figure 8-77. DQ/DM Routing With Any Number of Allowed DDR3 Devices

8.13.4.2.4.13 Routing Specification

8.13.4.2.4.13.1 CK and ADDR_CTRL Routing Specification

Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this

skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter

traces up to the length of the longest net in the net class and its associated clock. A metric to establish

this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the

length between the points when connecting them only with horizontal or vertical segments. A reasonable

trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address

Control Longest Manhattan distance.

Given the clock and address pin locations on the processor and the DDR3 memories, the maximum

possible Manhattan distance can be determined given the placement. Figure 8-78 and Figure 8-79 show

this distance for four loads and two loads, respectively. It is from this distance that the specifications on

the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly

for other address bus configurations; i.e., it is based on the longest net of the CK/ADDR_CTRL net class.

For CK and ADDR_CTRL routing, these specifications are contained in Table 8-75.

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TMS320DM814X Datasheet(PDF) 320 Page - Texas Instruments